3Com90xConstants.h

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef NIC_3COM90X_CONSTANTS_H
#define NIC_3COM90X_CONSTANTS_H

#define MAX_PACKET_SIZE 0xFFFF

#define NUM_UPDS 32

#define XCVR_MAGIC (0x5A00)

#define XMIT_RETRIES 2  // 250

/*** Register definitions for the 3c905 ***/
enum Registers
{
    regPowerMgmtCtrl_w = 0x7c,    
    regUpMaxBurst_w = 0x7a,       
    regDnMaxBurst_w = 0x78,       
    regDebugControl_w = 0x74,     
    regDebugData_l = 0x70,        
    regRealTimeCnt_l = 0x40,      
    regUpBurstThresh_b = 0x3e,    
    regUpPoll_b = 0x3d,           
    regUpPriorityThresh_b = 0x3c, 
    regUpListPtr_l = 0x38,        
    regCountdown_w = 0x36,        
    regFreeTimer_w = 0x34,        
    regUpPktStatus_l = 0x30,      
    regTxFreeThresh_b = 0x2f,     
    regDnPoll_b = 0x2d,           
    regDnPriorityThresh_b = 0x2c, 
    regDnBurstThresh_b = 0x2a,    
    regDnListPtr_l = 0x24,        
    regDmaCtrl_l = 0x20,          
    regIntStatusAuto_w = 0x1e,    
    regTxStatus_b = 0x1b,         
    regTimer_b = 0x1a,            
    regTxPktId_b = 0x18,          
    regCommandIntStatus_w = 0x0e, 
};

enum Registers7
{
    regPowerMgmtEvent_7_w = 0x0c, 
    regVlanEtherType_7_w = 0x04,  
    regVlanMask_7_w = 0x00,       
};

enum Registers6
{
    regBytesXmittedOk_6_w = 0x0c,     
    regBytesRcvdOk_6_w = 0x0a,        
    regUpperFramesOk_6_b = 0x09,      
    regFramesDeferred_6_b = 0x08,     
    regFramesRecdOk_6_b = 0x07,       
    regFramesXmittedOk_6_b = 0x06,    
    regRxOverruns_6_b = 0x05,         
    regLateCollisions_6_b = 0x04,     
    regSingleCollisions_6_b = 0x03,   
    regMultipleCollisions_6_b = 0x02, 
    regSqeErrors_6_b = 0x01,          
    regCarrierLost_6_b = 0x00,        
};

enum Registers5
{
    regIndicationEnable_5_w = 0x0c, 
    regInterruptEnable_5_w = 0x0a,  
    regTxReclaimThresh_5_b = 0x09,  
    regRxFilter_5_b = 0x08,         
    regRxEarlyThresh_5_w = 0x06,    
    regTxStartThresh_5_w = 0x00,    
};

enum Registers4
{
    regUpperBytesOk_4_b = 0x0d,      
    regBadSSD_4_b = 0x0c,            
    regMediaStatus_4_w = 0x0a,       
    regPhysicalMgmt_4_w = 0x08,      
    regNetworkDiagnostic_4_w = 0x06, 
    regFifoDiagnostic_4_w = 0x04,    
    regVcoDiagnostic_4_w = 0x02,     
};

enum Registers3
{
    regTxFree_3_w = 0x0c,            
    regRxFree_3_w = 0x0a,            
    regResetMediaOptions_3_w = 0x08, 
    regMacControl_3_w = 0x06,        
    regMaxPktSize_3_w = 0x04,        
    regInternalConfig_3_l = 0x00,    
};

enum Registers2
{
    regResetOptions_2_w = 0x0c,    
    regStationMask_2_3w = 0x06,    
    regStationAddress_2_3w = 0x00, 
};

enum Registers1
{
    regRxStatus_1_w = 0x0a, 
};

enum Registers0
{
    regEepromData_0_w = 0x0c,    
    regEepromCommand_0_w = 0x0a, 
    regBiosRomData_0_b = 0x08,   
    regBiosRomAddr_0_l = 0x04,   
};

/*** The names for the eight register windows ***/
enum Windows
{
    winPowerVlan7 = 0x07,
    winStatistics6 = 0x06,
    winTxRxControl5 = 0x05,
    winDiagnostics4 = 0x04,
    winTxRxOptions3 = 0x03,
    winAddressing2 = 0x02,
    winUnused1 = 0x01,
    winEepromBios0 = 0x00,
};

/*** Command definitions for the 3c90X ***/
enum Commands
{
    cmdGlobalReset = 0x00,          
    cmdSelectRegisterWindow = 0x01, 
    cmdEnableDcConverter = 0x02,    
    cmdRxDisable = 0x03,            
    cmdRxEnable = 0x04,             
    cmdRxReset = 0x05,              
    cmdStallCtl = 0x06,             
    cmdTxEnable = 0x09,             
    cmdTxDisable = 0x0A,            
    cmdTxReset = 0x0B,              
    cmdRequestInterrupt = 0x0C,     
    cmdAcknowledgeInterrupt = 0x0D, 
    cmdSetInterruptEnable = 0x0E,   
    cmdSetIndicationEnable = 0x0F,  
    cmdSetRxFilter = 0x10,          
    cmdSetRxEarlyThresh = 0x11,     
    cmdSetTxStartThresh = 0x13,     
    cmdStatisticsEnable = 0x15,     
    cmdStatisticsDisable = 0x16,    
    cmdDisableDcConverter = 0x17,   
    cmdSetTxReclaimThresh = 0x18,   
    cmdSetHashFilterBit = 0x19,     
};

/*** Values for int status register bitmask **/
#define INT_INTERRUPTLATCH (1 << 0)
#define INT_HOSTERROR (1 << 1)
#define INT_TXCOMPLETE (1 << 2)
#define INT_RXCOMPLETE (1 << 4)
#define INT_RXEARLY (1 << 5)
#define INT_INTREQUESTED (1 << 6)
#define INT_UPDATESTATS (1 << 7)
#define INT_LINKEVENT (1 << 8)
#define INT_DNCOMPLETE (1 << 9)
#define INT_UPCOMPLETE (1 << 10)
#define INT_DMAINPROGRESS (1 << 11)
#define INT_CMDINPROGRESS (1 << 12)
#define INT_WINDOWNUMBER (7 << 13)

#define ENABLED_INTS                                                     \
    (INT_UPCOMPLETE | INT_UPDATESTATS | INT_HOSTERROR | INT_DNCOMPLETE | \
     INT_TXCOMPLETE | INT_INTERRUPTLATCH)

#endif