The Pedigree Project  0.1
Rtl8139Constants.h
1 /*
2  * Copyright (c) 2008-2014, Pedigree Developers
3  *
4  * Please see the CONTRIB file in the root of the source tree for a full
5  * list of contributors.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
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10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef RTL8139_CONSTANTS_H
21 #define RTL8139_CONSTANTS_H
22 
23 enum Rtl8139Constants
24 {
25  RTL_MAC = 0, // MAC addresses registers
26  RTL_MAR = 8, // Multicast addresses registers
27  RTL_TXSTS0 = 0x10, // Tx Status register
28  RTL_TXADDR0 = 0x20, // Tx Address register
29  RTL_RXBUFF = 0x30, // Rx Buffer address register
30  RTL_CMD = 0x37, // Command register
31  RTL_RXCURR = 0x38, // Rx Buffer current offset register
32  RTL_IMR = 0x3C, // Intrerrupt Mask register
33  RTL_ISR = 0x3E, // Intrerrupt Status register
34  RTL_TXCFG = 0x40, // Tx Config register
35  RTL_RXCFG = 0x44, // Rx Config register
36  RTL_RXMIS = 0x4C, // Rx Missed register
37  RTL_CFG9346 = 0x50, // 9346 Config register
38  RTL_CFG1 = 0x52, // Config1 register
39  RTL_MSR = 0x58, // Media Status register
40  RTL_BMCR = 0x62, // Basic Mode Control register
41 
42  RTL_CMD_RES = 0x10, // Reset command
43  RTL_CMD_RXEN = 0x08, // Rx Enable command
44  RTL_CMD_TXEN = 0x04, // Tx Enable command
45 
46  RTL_ISR_TXERR = 0x08, // Tx Error irq status bit
47  RTL_ISR_TXOK = 0x04, // Tx OK irq status bit
48  RTL_ISR_RXERR = 0x02, // Rx Error irq status bit
49  RTL_ISR_RXOK = 0x01, // Rx OK irq status bit
50 
51  RTL_IMR_TXERR = 0x08, // Tx Error irq mask bit
52  RTL_IMR_TXOK = 0x04, // Tx OK irq mask bit
53  RTL_IMR_RXERR = 0x02, // Rx Error irq mask bit
54  RTL_IMR_RXOK = 0x01, // Rx OK irq mask bit
55 
56  RTL_RXCFG_FTH_NONE = 0xE000, // No FIFO treshhold
57  RTL_RXCFG_RBLN_64K = 0x1800, // 64K Rx Buffer length
58  RTL_RXCFG_MDMA_UNLM = 0x700, // Unlimited DMA Burst size
59  RTL_RXCFG_AR = 0x10, // Accept Runt packets
60  RTL_RXCFG_AB = 0x08, // Accept Broadcast packets
61  RTL_RXCFG_AM = 0x04, // Accept Multicast packets
62  RTL_RXCFG_APM = 0x02, // Accept Physical Match packets
63  RTL_RXCFG_AAP = 0x01, // Accept All packets
64 
65  RTL_RXSTS_MAR = 0x8000, // Multicast address
66  RTL_RXSTS_PAM = 0x4000, // Physical address matched
67  RTL_RXSTS_BAR = 0x2000, // Broadcast address
68  RTL_RXSTS_ISE = 0x20, // Invalid Symbol error
69  RTL_RXSTS_RUNT = 0x10, // Runt packet
70  RTL_RXSTS_LONG = 0x08, // Long packet
71  RTL_RXSTS_CRC = 0x04, // CRC error
72  RTL_RXSTS_FAE = 0x02, // Frame Alignment error
73  RTL_RXSTS_RXOK = 0x01, // Rx OK
74 
75  RTL_TXCFG_MDMA_1K = 0x600, // 1K DMA Burst
76  RTL_TXCFG_MDMA_2K = 0x700, // 2K DMA Burst
77  RTL_TXCFG_RR_48 = 0x20, // 48 (16 + 2 * 16) Tx Retry count
78 
79  RTL_CFG9346_LOCK = 0x00, // Lock BMCR registers
80  RTL_CFG9346_UNLOCK = 0xC0, // Unlock BMCR registers
81 
82  RTL_MSR_RXFCE = 0x40, // Rx Flow Control Enable bit
83  RTL_MSR_LINK = 0x4, // Inverse of Link Status bit
84 
85  RTL_BMCR_SPEED = 0x2000, // Speed(100Mbps/10Mbps) bit
86  RTL_BMCR_ANE = 0x1000, // Auto Negotiation Enable bit
87  RTL_BMCR_DUPLEX = 0x100, // Speed(100Mbps/10Mbps) bit
88 
89  RTL_BUFF_SIZE = 0x10000, // The size of the Rx and Tx buffers
90 
91  RTL_PACK_MAX = 0xFFFF, // The maximal size of a packet
92  RTL_PACK_MIN = 0x16, // The minimal size of a packet
93 };
94 
95 #endif
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