mips32/Processor.cc

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "pedigree/kernel/processor/Processor.h"
#include "InterruptManager.h"
#include "pedigree/kernel/processor/TlbManager.h"

void Processor::initialise1(const BootstrapStruct_t &Info)
{
    // Initialise this processor's interrupt handling
    MIPS32InterruptManager::initialiseProcessor();

    // TODO: Initialise the physical memory-management
    TlbManager::instance().initialise();

    //   m_Initialised = 1;
}

void Processor::initialise2(const BootstrapStruct_t &Info)
{
    // TODO

    //   m_Initialised = 2;
}

void Processor::identify(HugeStaticString &str)
{
    // Get the processor ID register.
    uint32_t prId = 0;
    asm volatile("mfc0 %0, $15; nop" : "=r"(prId));
    str += prId;
}