The Pedigree Project  0.1
nv_macros.h
1 /*
2  * Copyright (c) 2008-2014, Pedigree Developers
3  *
4  * Please see the CONTRIB file in the root of the source tree for a full
5  * list of contributors.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 /* NV registers definitions and macros for access to them */
21 
22 /* PCI_config_space */
23 #define NVCFG_DEVID 0x00
24 #define NVCFG_DEVCTRL 0x04
25 #define NVCFG_CLASS 0x08
26 #define NVCFG_HEADER 0x0c
27 #define NVCFG_BASE1REGS 0x10
28 #define NVCFG_BASE2FB 0x14
29 #define NVCFG_BASE3 0x18
30 #define NVCFG_BASE4 0x1c // unknown if used
31 #define NVCFG_BASE5 0x20 // unknown if used
32 #define NVCFG_BASE6 0x24 // unknown if used
33 #define NVCFG_BASE7 0x28 // unknown if used
34 #define NVCFG_SUBSYSID1 0x2c
35 #define NVCFG_ROMBASE 0x30
36 #define NVCFG_CAPPTR 0x34
37 #define NVCFG_CFG_1 0x38 // unknown if used
38 #define NVCFG_INTERRUPT 0x3c
39 #define NVCFG_SUBSYSID2 0x40
40 #define NVCFG_AGPREF 0x44
41 #define NVCFG_AGPSTAT 0x48
42 #define NVCFG_AGPCMD 0x4c
43 #define NVCFG_ROMSHADOW 0x50
44 #define NVCFG_VGA 0x54
45 #define NVCFG_SCHRATCH 0x58
46 #define NVCFG_CFG_10 0x5c
47 #define NVCFG_CFG_11 0x60
48 #define NVCFG_CFG_12 0x64
49 #define NVCFG_CFG_13 0x68 // unknown if used
50 #define NVCFG_CFG_14 0x6c // unknown if used
51 #define NVCFG_CFG_15 0x70 // unknown if used
52 #define NVCFG_CFG_16 0x74 // unknown if used
53 #define NVCFG_PCIEREF 0x78
54 #define NVCFG_PCIEDCAP 0x7c
55 #define NVCFG_PCIEDCTST 0x80
56 #define NVCFG_PCIELCAP 0x84
57 #define NVCFG_PCIELCTST 0x88
58 #define NVCFG_CFG_22 0x8c // unknown if used
59 #define NVCFG_CFG_23 0x90 // unknown if used
60 #define NVCFG_CFG_24 0x94 // unknown if used
61 #define NVCFG_CFG_25 0x98 // unknown if used
62 #define NVCFG_CFG_26 0x9c // unknown if used
63 #define NVCFG_CFG_27 0xa0 // unknown if used
64 #define NVCFG_CFG_28 0xa4 // unknown if used
65 #define NVCFG_CFG_29 0xa8 // unknown if used
66 #define NVCFG_CFG_30 0xac // unknown if used
67 #define NVCFG_CFG_31 0xb0 // unknown if used
68 #define NVCFG_CFG_32 0xb4 // unknown if used
69 #define NVCFG_CFG_33 0xb8 // unknown if used
70 #define NVCFG_CFG_34 0xbc // unknown if used
71 #define NVCFG_CFG_35 0xc0 // unknown if used
72 #define NVCFG_CFG_36 0xc4 // unknown if used
73 #define NVCFG_CFG_37 0xc8 // unknown if used
74 #define NVCFG_CFG_38 0xcc // unknown if used
75 #define NVCFG_CFG_39 0xd0 // unknown if used
76 #define NVCFG_CFG_40 0xd4 // unknown if used
77 #define NVCFG_CFG_41 0xd8 // unknown if used
78 #define NVCFG_CFG_42 0xdc // unknown if used
79 #define NVCFG_CFG_43 0xe0 // unknown if used
80 #define NVCFG_CFG_44 0xe4 // unknown if used
81 #define NVCFG_CFG_45 0xe8 // unknown if used
82 #define NVCFG_CFG_46 0xec // unknown if used
83 #define NVCFG_CFG_47 0xf0 // unknown if used
84 #define NVCFG_CFG_48 0xf4 // unknown if used
85 #define NVCFG_CFG_49 0xf8 // unknown if used
86 #define NVCFG_CFG_50 0xfc // unknown if used
87 
88 /* used NV INT registers for vblank */
89 #define NV32_MAIN_INTE 0x00000140
90 #define NV32_CRTC_INTS 0x00600100
91 #define NV32_CRTC_INTE 0x00600140
92 #define NV32_CRTC2_INTS 0x00602100
93 #define NV32_CRTC2_INTE 0x00602140
94 
95 /* NV ACCeleration registers */
96 /* engine initialisation registers */
97 #define NVACC_ABS_UCLP_XMIN 0x0040053c
98 #define NVACC_ABS_UCLP_YMIN 0x00400540
99 #define NVACC_ABS_UCLP_XMAX 0x00400544
100 #define NVACC_ABS_UCLP_YMAX 0x00400548
101 #define NVACC_BETA_AND_VAL 0x00400608
102 #define NVACC_FORMATS 0x00400618
103 #define NVACC_OFFSET0 0x00400640
104 #define NVACC_OFFSET1 0x00400644
105 #define NVACC_OFFSET2 0x00400648
106 #define NVACC_OFFSET3 0x0040064c
107 #define NVACC_OFFSET4 0x00400650
108 #define NVACC_OFFSET5 0x00400654
109 #define NVACC_BBASE0 0x00400658
110 #define NVACC_BBASE1 0x0040065c
111 #define NVACC_BBASE2 0x00400660
112 #define NVACC_BBASE3 0x00400664
113 #define NVACC_NV10_BBASE4 0x00400668
114 #define NVACC_NV10_BBASE5 0x0040066c
115 #define NVACC_PITCH0 0x00400670
116 #define NVACC_PITCH1 0x00400674
117 #define NVACC_PITCH2 0x00400678
118 #define NVACC_PITCH3 0x0040067c
119 #define NVACC_PITCH4 0x00400680
120 #define NVACC_BLIMIT0 0x00400684
121 #define NVACC_BLIMIT1 0x00400688
122 #define NVACC_BLIMIT2 0x0040068c
123 #define NVACC_BLIMIT3 0x00400690
124 #define NVACC_NV10_BLIMIT4 0x00400694
125 #define NVACC_NV10_BLIMIT5 0x00400698
126 #define NVACC_BPIXEL 0x00400724
127 #define NVACC_NV20_OFFSET0 0x00400820
128 #define NVACC_NV20_OFFSET1 0x00400824
129 #define NVACC_NV20_OFFSET2 0x00400828
130 #define NVACC_NV20_OFFSET3 0x0040082c
131 #define NVACC_STRD_FMT 0x00400830
132 #define NVACC_NV20_PITCH0 0x00400850
133 #define NVACC_NV20_PITCH1 0x00400854
134 #define NVACC_NV20_PITCH2 0x00400858
135 #define NVACC_NV20_PITCH3 0x0040085c
136 #define NVACC_NV20_BLIMIT6 0x00400864
137 #define NVACC_NV20_BLIMIT7 0x00400868
138 #define NVACC_NV20_BLIMIT8 0x0040086c
139 #define NVACC_NV20_BLIMIT9 0x00400870
140 #define NVACC_NV25_WHAT1 0x00400890
141 
142 /* specials */
143 #define NVACC_DEBUG0 0x00400080
144 #define NVACC_DEBUG1 0x00400084
145 #define NVACC_DEBUG2 0x00400088
146 #define NVACC_DEBUG3 0x0040008c
147 #define NVACC_NV10_DEBUG4 0x00400090
148 #define NVACC_NV10_DEBUG5 0x00400094
149 #define NVACC_NV20_WHAT5 0x00400098
150 #define NVACC_NV20_WHAT1 0x0040009c
151 #define NVACC_ACC_INTS 0x00400100
152 #define NVACC_ACC_INTE 0x00400140
153 #define NVACC_NV10_CTX_CTRL 0x00400144
154 #define NVACC_NV4X_DMA_SRC 0x00400220
155 #define NVACC_NV4X_WHAT1 0x0040032c
156 #define NVACC_NV4X_WHAT2 0x00405000
157 #define NVACC_NV25_WHAT0 0x00400610
158 #define NVACC_STATUS 0x00400700
159 #define NVACC_NV04_SURF_TYP 0x0040070c
160 #define NVACC_NV10_SURF_TYP 0x00400710
161 #define NVACC_NV04_ACC_STAT 0x00400710
162 #define NVACC_NV10_ACC_STAT 0x00400714
163 #define NVACC_FIFO_EN 0x00400720
164 #define NVACC_RDI_INDEX 0x00400750
165 #define NVACC_RDI_DATA 0x00400754
166 #define NVACC_PAT_SHP 0x00400810
167 #define NVACC_NV40P_WHAT0 0x00400820
168 #define NVACC_NV40P_WHAT1 0x00400824
169 #define NVACC_NV40P_WHAT2 0x00400828
170 #define NVACC_NV40P_WHAT3 0x0040082c
171 #define NVACC_NV40P_OFFSET0 0x00400840
172 #define NVACC_NV40P_OFFSET1 0x00400844
173 #define NVACC_NV44_WHAT2 0x00400860
174 #define NVACC_NV44_WHAT3 0x00400864
175 // fixme? (guessed)
176 #define NVACC_NV40P_PITCH0 0x00400870
177 #define NVACC_NV40P_PITCH1 0x00400874
178 #define NVACC_NV20_WHAT2 0x00400880
179 // end fixme.
180 #define NVACC_NV40P_BLIMIT6 0x004008a0
181 #define NVACC_NV40P_BLIMIT7 0x004008a4
182 #define NVACC_NV20_WHAT0 0x00400900
183 #define NVACC_NV41_WHAT0 0x00400d00
184 #define NVACC_NV20_2_WHAT0 0x00406900
185 #define NVACC_NV40_WHAT0 0x004009b0
186 #define NVACC_NV40_WHAT1 0x004009b4
187 #define NVACC_NV40_WHAT2 0x004009b8
188 #define NVACC_NV40_WHAT3 0x004009bc
189 #define NVACC_NV20_WHAT3 0x00400b80
190 #define NVACC_NV20_WHAT4 0x00400b84
191 #define NVACC_NV25_WHAT2 0x00400b88
192 #define NVACC_WINCLIP_H_0 0x00400f00
193 #define NVACC_WINCLIP_H_1 0x00400f04
194 #define NVACC_WINCLIP_H_2 0x00400f08
195 #define NVACC_WINCLIP_H_3 0x00400f0c
196 #define NVACC_WINCLIP_H_4 0x00400f10
197 #define NVACC_WINCLIP_H_5 0x00400f14
198 #define NVACC_WINCLIP_H_6 0x00400f18
199 #define NVACC_WINCLIP_H_7 0x00400f1c
200 #define NVACC_WINCLIP_V_0 0x00400f20
201 #define NVACC_WINCLIP_V_1 0x00400f24
202 #define NVACC_WINCLIP_V_2 0x00400f28
203 #define NVACC_WINCLIP_V_3 0x00400f2c
204 #define NVACC_WINCLIP_V_4 0x00400f30
205 #define NVACC_WINCLIP_V_5 0x00400f34
206 #define NVACC_WINCLIP_V_6 0x00400f38
207 #define NVACC_WINCLIP_V_7 0x00400f3c
208 #define NVACC_NV10_XFMOD0 0x00400f40
209 #define NVACC_NV10_XFMOD1 0x00400f44
210 #define NVACC_GLOB_STAT_0 0x00400f48
211 #define NVACC_GLOB_STAT_1 0x00400f4c
212 #define NVACC_NV10_PIPEADR 0x00400f50
213 #define NVACC_NV10_PIPEDAT 0x00400f54
214 /* PGRAPH unknown registers */
215 #define NVACC_PGWHAT_00 0x00400e00
216 #define NVACC_PGWHAT_01 0x00400e04
217 #define NVACC_PGWHAT_02 0x00400e08
218 #define NVACC_PGWHAT_03 0x00400e0c
219 #define NVACC_PGWHAT_04 0x00400e10
220 #define NVACC_PGWHAT_05 0x00400e14
221 #define NVACC_PGWHAT_06 0x00400e18
222 #define NVACC_PGWHAT_07 0x00400e1c
223 #define NVACC_PGWHAT_08 0x00400e20
224 #define NVACC_PGWHAT_09 0x00400e24
225 #define NVACC_PGWHAT_0A 0x00400e28
226 #define NVACC_PGWHAT_0B 0x00400e2c
227 #define NVACC_PGWHAT_0C 0x00400e30
228 #define NVACC_PGWHAT_0D 0x00400e34
229 #define NVACC_PGWHAT_0E 0x00400e38
230 #define NVACC_PGWHAT_0F 0x00400e3c
231 #define NVACC_PGWHAT_10 0x00400e40
232 #define NVACC_PGWHAT_11 0x00400e44
233 #define NVACC_PGWHAT_12 0x00400e48
234 #define NVACC_PGWHAT_13 0x00400e4c
235 #define NVACC_PGWHAT_14 0x00400e50
236 #define NVACC_PGWHAT_15 0x00400e54
237 #define NVACC_PGWHAT_16 0x00400e58
238 #define NVACC_PGWHAT_17 0x00400e5c
239 #define NVACC_PGWHAT_18 0x00400e60
240 #define NVACC_PGWHAT_19 0x00400e64
241 #define NVACC_PGWHAT_1A 0x00400e68
242 #define NVACC_PGWHAT_1B 0x00400e6c
243 #define NVACC_PGWHAT_1C 0x00400e70
244 #define NVACC_PGWHAT_1D 0x00400e74
245 #define NVACC_PGWHAT_1E 0x00400e78
246 #define NVACC_PGWHAT_1F 0x00400e7c
247 #define NVACC_PGWHAT_20 0x00400e80
248 #define NVACC_PGWHAT_21 0x00400e84
249 #define NVACC_PGWHAT_22 0x00400e88
250 #define NVACC_PGWHAT_23 0x00400e8c
251 #define NVACC_PGWHAT_24 0x00400e90
252 #define NVACC_PGWHAT_25 0x00400e94
253 #define NVACC_PGWHAT_26 0x00400e98
254 #define NVACC_PGWHAT_27 0x00400e9c
255 #define NVACC_PGWHAT_28 0x00400ea0
256 #define NVACC_PGWHAT_29 0x00400ea4
257 #define NVACC_PGWHAT_2A 0x00400ea8
258 /* PGRAPH cache registers */
259 #define NVACC_CACHE1_1 0x00400160
260 #define NVACC_CACHE1_2 0x00400180
261 #define NVACC_CACHE1_3 0x004001a0
262 #define NVACC_CACHE1_4 0x004001c0
263 #define NVACC_CACHE1_5 0x004001e0
264 #define NVACC_CACHE2_1 0x00400164
265 #define NVACC_CACHE2_2 0x00400184
266 #define NVACC_CACHE2_3 0x004001a4
267 #define NVACC_CACHE2_4 0x004001c4
268 #define NVACC_CACHE2_5 0x004001e4
269 #define NVACC_CACHE3_1 0x00400168
270 #define NVACC_CACHE3_2 0x00400188
271 #define NVACC_CACHE3_3 0x004001a8
272 #define NVACC_CACHE3_4 0x004001c8
273 #define NVACC_CACHE3_5 0x004001e8
274 #define NVACC_CACHE4_1 0x0040016c
275 #define NVACC_CACHE4_2 0x0040018c
276 #define NVACC_CACHE4_3 0x004001ac
277 #define NVACC_CACHE4_4 0x004001cc
278 #define NVACC_CACHE4_5 0x004001ec
279 #define NVACC_NV10_CACHE5_1 0x00400170
280 #define NVACC_NV04_CTX_CTRL 0x00400170
281 #define NVACC_CACHE5_2 0x00400190
282 #define NVACC_CACHE5_3 0x004001b0
283 #define NVACC_CACHE5_4 0x004001d0
284 #define NVACC_CACHE5_5 0x004001f0
285 #define NVACC_NV10_CACHE6_1 0x00400174
286 #define NVACC_CACHE6_2 0x00400194
287 #define NVACC_CACHE6_3 0x004001b4
288 #define NVACC_CACHE6_4 0x004001d4
289 #define NVACC_CACHE6_5 0x004001f4
290 #define NVACC_NV10_CACHE7_1 0x00400178
291 #define NVACC_CACHE7_2 0x00400198
292 #define NVACC_CACHE7_3 0x004001b8
293 #define NVACC_CACHE7_4 0x004001d8
294 #define NVACC_CACHE7_5 0x004001f8
295 #define NVACC_NV10_CACHE8_1 0x0040017c
296 #define NVACC_CACHE8_2 0x0040019c
297 #define NVACC_CACHE8_3 0x004001bc
298 #define NVACC_CACHE8_4 0x004001dc
299 #define NVACC_CACHE8_5 0x004001fc
300 #define NVACC_NV10_CTX_SW1 0x0040014c
301 #define NVACC_NV10_CTX_SW2 0x00400150
302 #define NVACC_NV10_CTX_SW3 0x00400154
303 #define NVACC_NV10_CTX_SW4 0x00400158
304 #define NVACC_NV10_CTX_SW5 0x0040015c
305 /* engine tile registers src */
306 #define NVACC_NV10_FBTIL0AD 0x00100240
307 #define NVACC_NV10_FBTIL0ED 0x00100244
308 #define NVACC_NV10_FBTIL0PT 0x00100248
309 #define NVACC_NV10_FBTIL0ST 0x0010024c
310 #define NVACC_NV10_FBTIL1AD 0x00100250
311 #define NVACC_NV10_FBTIL1ED 0x00100254
312 #define NVACC_NV10_FBTIL1PT 0x00100258
313 #define NVACC_NV10_FBTIL1ST 0x0010025c
314 #define NVACC_NV10_FBTIL2AD 0x00100260
315 #define NVACC_NV10_FBTIL2ED 0x00100264
316 #define NVACC_NV10_FBTIL2PT 0x00100268
317 #define NVACC_NV10_FBTIL2ST 0x0010026c
318 #define NVACC_NV10_FBTIL3AD 0x00100270
319 #define NVACC_NV10_FBTIL3ED 0x00100274
320 #define NVACC_NV10_FBTIL3PT 0x00100278
321 #define NVACC_NV10_FBTIL3ST 0x0010027c
322 #define NVACC_NV10_FBTIL4AD 0x00100280
323 #define NVACC_NV10_FBTIL4ED 0x00100284
324 #define NVACC_NV10_FBTIL4PT 0x00100288
325 #define NVACC_NV10_FBTIL4ST 0x0010028c
326 #define NVACC_NV10_FBTIL5AD 0x00100290
327 #define NVACC_NV10_FBTIL5ED 0x00100294
328 #define NVACC_NV10_FBTIL5PT 0x00100298
329 #define NVACC_NV10_FBTIL5ST 0x0010029c
330 #define NVACC_NV10_FBTIL6AD 0x001002a0
331 #define NVACC_NV10_FBTIL6ED 0x001002a4
332 #define NVACC_NV10_FBTIL6PT 0x001002a8
333 #define NVACC_NV10_FBTIL6ST 0x001002ac
334 #define NVACC_NV10_FBTIL7AD 0x001002b0
335 #define NVACC_NV10_FBTIL7ED 0x001002b4
336 #define NVACC_NV10_FBTIL7PT 0x001002b8
337 #define NVACC_NV10_FBTIL7ST 0x001002bc
338 #define NVACC_NV41_FBTIL0AD 0x00100600
339 #define NVACC_NV41_FBTIL0ED 0x00100604
340 #define NVACC_NV41_FBTIL0PT 0x00100608
341 #define NVACC_NV41_FBTIL0ST 0x0010060c
342 #define NVACC_NV41_FBTIL1AD 0x00100610
343 #define NVACC_NV41_FBTIL1ED 0x00100614
344 #define NVACC_NV41_FBTIL1PT 0x00100618
345 #define NVACC_NV41_FBTIL1ST 0x0010061c
346 #define NVACC_NV41_FBTIL2AD 0x00100620
347 #define NVACC_NV41_FBTIL2ED 0x00100624
348 #define NVACC_NV41_FBTIL2PT 0x00100628
349 #define NVACC_NV41_FBTIL2ST 0x0010062c
350 #define NVACC_NV41_FBTIL3AD 0x00100630
351 #define NVACC_NV41_FBTIL3ED 0x00100634
352 #define NVACC_NV41_FBTIL3PT 0x00100638
353 #define NVACC_NV41_FBTIL3ST 0x0010063c
354 #define NVACC_NV41_FBTIL4AD 0x00100640
355 #define NVACC_NV41_FBTIL4ED 0x00100644
356 #define NVACC_NV41_FBTIL4PT 0x00100648
357 #define NVACC_NV41_FBTIL4ST 0x0010064c
358 #define NVACC_NV41_FBTIL5AD 0x00100650
359 #define NVACC_NV41_FBTIL5ED 0x00100654
360 #define NVACC_NV41_FBTIL5PT 0x00100658
361 #define NVACC_NV41_FBTIL5ST 0x0010065c
362 #define NVACC_NV41_FBTIL6AD 0x00100660
363 #define NVACC_NV41_FBTIL6ED 0x00100664
364 #define NVACC_NV41_FBTIL6PT 0x00100668
365 #define NVACC_NV41_FBTIL6ST 0x0010066c
366 #define NVACC_NV41_FBTIL7AD 0x00100670
367 #define NVACC_NV41_FBTIL7ED 0x00100674
368 #define NVACC_NV41_FBTIL7PT 0x00100678
369 #define NVACC_NV41_FBTIL7ST 0x0010067c
370 #define NVACC_NV41_FBTIL8AD 0x00100680
371 #define NVACC_NV41_FBTIL8ED 0x00100684
372 #define NVACC_NV41_FBTIL8PT 0x00100688
373 #define NVACC_NV41_FBTIL8ST 0x0010068c
374 #define NVACC_NV41_FBTIL9AD 0x00100690
375 #define NVACC_NV41_FBTIL9ED 0x00100694
376 #define NVACC_NV41_FBTIL9PT 0x00100698
377 #define NVACC_NV41_FBTIL9ST 0x0010069c
378 #define NVACC_NV41_FBTILAAD 0x001006a0
379 #define NVACC_NV41_FBTILAED 0x001006a4
380 #define NVACC_NV41_FBTILAPT 0x001006a8
381 #define NVACC_NV41_FBTILAST 0x001006ac
382 #define NVACC_NV41_FBTILBAD 0x001006b0
383 #define NVACC_NV41_FBTILBED 0x001006b4
384 #define NVACC_NV41_FBTILBPT 0x001006b8
385 #define NVACC_NV41_FBTILBST 0x001006bc
386 #define NVACC_G70_FBTILCAD 0x001006c0
387 #define NVACC_G70_FBTILCED 0x001006c4
388 #define NVACC_G70_FBTILCPT 0x001006c8
389 #define NVACC_G70_FBTILCST 0x001006cc
390 #define NVACC_G70_FBTILDAD 0x001006d0
391 #define NVACC_G70_FBTILDED 0x001006d4
392 #define NVACC_G70_FBTILDPT 0x001006d8
393 #define NVACC_G70_FBTILDST 0x001006dc
394 #define NVACC_G70_FBTILEAD 0x001006e0
395 #define NVACC_G70_FBTILEED 0x001006e4
396 #define NVACC_G70_FBTILEPT 0x001006e8
397 #define NVACC_G70_FBTILEST 0x001006ec
398 /* engine tile registers dst */
399 #define NVACC_NV20_WHAT_T0 0x004009a4
400 #define NVACC_NV20_WHAT_T1 0x004009a8
401 #define NVACC_NV40_WHAT_T2 0x004069a4
402 #define NVACC_NV40_WHAT_T3 0x004069a8
403 #define NVACC_NV40P_WHAT_T0 0x004009f0
404 #define NVACC_NV40P_WHAT_T1 0x004009f4
405 #define NVACC_G70_WHAT_T0 0x00400df0
406 #define NVACC_G70_WHAT_T1 0x00400df4
407 #define NVACC_NV40P_WHAT_T2 0x004069f0
408 #define NVACC_NV40P_WHAT_T3 0x004069f4
409 #define NVACC_NV10_TIL0AD 0x00400b00
410 #define NVACC_NV10_TIL0ED 0x00400b04
411 #define NVACC_NV10_TIL0PT 0x00400b08
412 #define NVACC_NV10_TIL0ST 0x00400b0c
413 #define NVACC_NV10_TIL1AD 0x00400b10
414 #define NVACC_NV10_TIL1ED 0x00400b14
415 #define NVACC_NV10_TIL1PT 0x00400b18
416 #define NVACC_NV10_TIL1ST 0x00400b1c
417 #define NVACC_NV10_TIL2AD 0x00400b20
418 #define NVACC_NV10_TIL2ED 0x00400b24
419 #define NVACC_NV10_TIL2PT 0x00400b28
420 #define NVACC_NV10_TIL2ST 0x00400b2c
421 #define NVACC_NV10_TIL3AD 0x00400b30
422 #define NVACC_NV10_TIL3ED 0x00400b34
423 #define NVACC_NV10_TIL3PT 0x00400b38
424 #define NVACC_NV10_TIL3ST 0x00400b3c
425 #define NVACC_NV10_TIL4AD 0x00400b40
426 #define NVACC_NV10_TIL4ED 0x00400b44
427 #define NVACC_NV10_TIL4PT 0x00400b48
428 #define NVACC_NV10_TIL4ST 0x00400b4c
429 #define NVACC_NV10_TIL5AD 0x00400b50
430 #define NVACC_NV10_TIL5ED 0x00400b54
431 #define NVACC_NV10_TIL5PT 0x00400b58
432 #define NVACC_NV10_TIL5ST 0x00400b5c
433 #define NVACC_NV10_TIL6AD 0x00400b60
434 #define NVACC_NV10_TIL6ED 0x00400b64
435 #define NVACC_NV10_TIL6PT 0x00400b68
436 #define NVACC_NV10_TIL6ST 0x00400b6c
437 #define NVACC_NV10_TIL7AD 0x00400b70
438 #define NVACC_NV10_TIL7ED 0x00400b74
439 #define NVACC_NV10_TIL7PT 0x00400b78
440 #define NVACC_NV10_TIL7ST 0x00400b7c
441 /* cache setup registers */
442 #define NVACC_PF_INTSTAT 0x00002100
443 #define NVACC_PF_INTEN 0x00002140
444 #define NVACC_PF_RAMHT 0x00002210
445 #define NVACC_PF_RAMFC 0x00002214
446 #define NVACC_PF_RAMRO 0x00002218
447 #define NVACC_PF_CACHES 0x00002500
448 #define NVACC_PF_MODE 0x00002504
449 #define NVACC_PF_SIZE 0x0000250c
450 #define NVACC_PF_CACH0_PSH0 0x00003000
451 #define NVACC_PF_CACH0_PUL0 0x00003050
452 #define NVACC_PF_CACH0_PUL1 0x00003054
453 #define NVACC_PF_CACH1_PSH0 0x00003200
454 #define NVACC_PF_CACH1_PSH1 0x00003204
455 #define NVACC_PF_CACH1_DMAS 0x00003220
456 #define NVACC_PF_CACH1_DMAF 0x00003224
457 #define NVACC_PF_CACH1_DMAI 0x0000322c
458 #define NVACC_PF_CACH1_DMAC 0x00003230
459 #define NVACC_PF_CACH1_DMAP 0x00003240
460 #define NVACC_PF_CACH1_DMAG 0x00003244
461 #define NVACC_PF_CACH1_PUL0 0x00003250
462 #define NVACC_PF_CACH1_PUL1 0x00003254
463 #define NVACC_PF_CACH1_HASH 0x00003258
464 #define NVACC_PF_CACH1_ENG 0x00003280
465 /* Ptimer registers */
466 #define NVACC_PT_INTSTAT 0x00009100
467 #define NVACC_PT_INTEN 0x00009140
468 #define NVACC_PT_NUMERATOR 0x00009200
469 #define NVACC_PT_DENOMINATR 0x00009210
470 /* used PRAMIN registers */
471 #define NVACC_PR_CTX0_R 0x00711400
472 #define NVACC_PR_CTX1_R 0x00711404
473 #define NVACC_PR_CTX2_R 0x00711408
474 #define NVACC_PR_CTX3_R 0x0071140c
475 #define NVACC_PR_CTX0_0 0x00711420
476 #define NVACC_PR_CTX1_0 0x00711424
477 #define NVACC_PR_CTX2_0 0x00711428
478 #define NVACC_PR_CTX3_0 0x0071142c
479 #define NVACC_PR_CTX0_1 0x00711430
480 #define NVACC_PR_CTX1_1 0x00711434
481 #define NVACC_PR_CTX2_1 0x00711438
482 #define NVACC_PR_CTX3_1 0x0071143c
483 #define NVACC_PR_CTX0_2 0x00711440
484 #define NVACC_PR_CTX1_2 0x00711444
485 #define NVACC_PR_CTX2_2 0x00711448
486 #define NVACC_PR_CTX3_2 0x0071144c
487 #define NVACC_PR_CTX0_3 0x00711450
488 #define NVACC_PR_CTX1_3 0x00711454
489 #define NVACC_PR_CTX2_3 0x00711458
490 #define NVACC_PR_CTX3_3 0x0071145c
491 #define NVACC_PR_CTX0_4 0x00711460
492 #define NVACC_PR_CTX1_4 0x00711464
493 #define NVACC_PR_CTX2_4 0x00711468
494 #define NVACC_PR_CTX3_4 0x0071146c
495 #define NVACC_PR_CTX0_5 0x00711470
496 #define NVACC_PR_CTX1_5 0x00711474
497 #define NVACC_PR_CTX2_5 0x00711478
498 #define NVACC_PR_CTX3_5 0x0071147c
499 #define NVACC_PR_CTX0_6 0x00711480
500 #define NVACC_PR_CTX1_6 0x00711484
501 #define NVACC_PR_CTX2_6 0x00711488
502 #define NVACC_PR_CTX3_6 0x0071148c
503 #define NVACC_PR_CTX0_7 0x00711490
504 #define NVACC_PR_CTX1_7 0x00711494
505 #define NVACC_PR_CTX2_7 0x00711498
506 #define NVACC_PR_CTX3_7 0x0071149c
507 #define NVACC_PR_CTX0_8 0x007114a0
508 #define NVACC_PR_CTX1_8 0x007114a4
509 #define NVACC_PR_CTX2_8 0x007114a8
510 #define NVACC_PR_CTX3_8 0x007114ac
511 #define NVACC_PR_CTX0_9 0x007114b0
512 #define NVACC_PR_CTX1_9 0x007114b4
513 #define NVACC_PR_CTX2_9 0x007114b8
514 #define NVACC_PR_CTX3_9 0x007114bc
515 #define NVACC_PR_CTX0_A 0x007114c0
516 #define NVACC_PR_CTX1_A 0x007114c4 /* not used */
517 #define NVACC_PR_CTX2_A 0x007114c8
518 #define NVACC_PR_CTX3_A 0x007114cc
519 #define NVACC_PR_CTX0_B 0x007114d0
520 #define NVACC_PR_CTX1_B 0x007114d4
521 #define NVACC_PR_CTX2_B 0x007114d8
522 #define NVACC_PR_CTX3_B 0x007114dc
523 #define NVACC_PR_CTX0_C 0x007114e0
524 #define NVACC_PR_CTX1_C 0x007114e4
525 #define NVACC_PR_CTX2_C 0x007114e8
526 #define NVACC_PR_CTX3_C 0x007114ec
527 #define NVACC_PR_CTX0_D 0x007114f0
528 #define NVACC_PR_CTX1_D 0x007114f4
529 #define NVACC_PR_CTX2_D 0x007114f8
530 #define NVACC_PR_CTX3_D 0x007114fc
531 #define NVACC_PR_CTX0_E 0x00711500
532 #define NVACC_PR_CTX1_E 0x00711504
533 #define NVACC_PR_CTX2_E 0x00711508
534 #define NVACC_PR_CTX3_E 0x0071150c
535 #define NVACC_PR_CTX0_F 0x00711510
536 #define NVACC_PR_CTX1_F 0x00711514
537 #define NVACC_PR_CTX2_F 0x00711518
538 #define NVACC_PR_CTX3_F 0x0071151c
539 #define NVACC_PR_CTX0_10 0x00711520
540 #define NVACC_PR_CTX1_10 0x00711524
541 #define NVACC_PR_CTX2_10 0x00711528
542 #define NVACC_PR_CTX3_10 0x0071152c
543 /* used RAMHT registers (hash-table) */
544 #define NVACC_HT_HANDL_00 0x00710000
545 #define NVACC_HT_VALUE_00 0x00710004
546 #define NVACC_HT_HANDL_01 0x00710008
547 #define NVACC_HT_VALUE_01 0x0071000c
548 #define NVACC_HT_HANDL_02 0x00710010
549 #define NVACC_HT_VALUE_02 0x00710014
550 #define NVACC_HT_HANDL_03 0x00710018
551 #define NVACC_HT_VALUE_03 0x0071001c
552 #define NVACC_HT_HANDL_04 0x00710020
553 #define NVACC_HT_VALUE_04 0x00710024
554 #define NVACC_HT_HANDL_05 0x00710028
555 #define NVACC_HT_VALUE_05 0x0071002c
556 #define NVACC_HT_HANDL_06 0x00710030
557 #define NVACC_HT_VALUE_06 0x00710034
558 #define NVACC_HT_HANDL_10 0x00710080
559 #define NVACC_HT_VALUE_10 0x00710084
560 #define NVACC_HT_HANDL_11 0x00710088
561 #define NVACC_HT_VALUE_11 0x0071008c
562 #define NVACC_HT_HANDL_12 0x00710090
563 #define NVACC_HT_VALUE_12 0x00710094
564 #define NVACC_HT_HANDL_13 0x00710098
565 #define NVACC_HT_VALUE_13 0x0071009c
566 #define NVACC_HT_HANDL_14 0x007100a0
567 #define NVACC_HT_VALUE_14 0x007100a4
568 #define NVACC_HT_HANDL_15 0x007100a8
569 #define NVACC_HT_VALUE_15 0x007100ac
570 #define NVACC_HT_HANDL_16 0x007100b0
571 #define NVACC_HT_VALUE_16 0x007100b4
572 #define NVACC_HT_HANDL_17 0x007100b8
573 #define NVACC_HT_VALUE_17 0x007100bc
574 
575 /* acc engine fifo setup registers (for function_register 'mappings') */
576 #define NVACC_FIFO 0x00800000
577 #define NVACC_FIFO_CH0 0x00800000
578 #define NVACC_FIFO_CH1 0x00802000
579 #define NVACC_FIFO_CH2 0x00804000
580 #define NVACC_FIFO_CH3 0x00806000
581 #define NVACC_FIFO_CH4 0x00808000
582 #define NVACC_FIFO_CH5 0x0080a000
583 #define NVACC_FIFO_CH6 0x0080c000
584 #define NVACC_FIFO_CH7 0x0080e000
585 
586 /* Nvidia PCI direct registers */
587 #define NV32_PWRUPCTRL 0x00000200
588 #define NV32_DUALHEAD_CTRL 0x000010f0 // verify!!!
589 #define NV8_MISCW 0x000c03c2
590 #define NV8_MISCR 0x000c03cc
591 #define NV8_VSE2 0x000c03c3
592 #define NV8_SEQIND 0x000c03c4
593 #define NV16_SEQIND 0x000c03c4
594 #define NV8_SEQDAT 0x000c03c5
595 #define NV8_GRPHIND 0x000c03ce
596 #define NV16_GRPHIND 0x000c03ce
597 #define NV8_GRPHDAT 0x000c03cf
598 
599 /* bootstrap info registers */
600 #define NV32_NV4STRAPINFO 0x00100000
601 #define NV32_PFB_CONFIG_0 0x00100200
602 #define NV32_PFB_CONFIG_1 0x00100204
603 #define NV32_NV10STRAPINFO 0x0010020c
604 #define NV32_FB_MRS1 0x001002c0
605 #define NV32_FB_MRS2 0x001002c8
606 #define NV32_PFB_CLS_PAGE2 0x0010033c
607 #define NV32_NVSTRAPINFO2 0x00101000
608 
609 /* registers needed for 'coldstart' */
610 #define NV32_PFB_DEBUG_0 0x00100080
611 #define NV32_PFB_REFCTRL 0x00100210
612 #define NV32_COREPLL 0x00680500
613 #define NV32_MEMPLL 0x00680504
614 #define NV32_PLL_CTRL 0x00680510
615 #define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */
616 #define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */
617 #define NV32_CONFIG 0x00600804
618 
619 /* primary head */
620 #define NV8_ATTRINDW 0x006013c0
621 #define NV8_ATTRDATW 0x006013c0
622 #define NV8_ATTRDATR 0x006013c1
623 #define NV8_CRTCIND 0x006013d4
624 #define NV16_CRTCIND 0x006013d4
625 #define NV8_CRTCDAT 0x006013d5
626 #define NV8_INSTAT1 0x006013da
627 #define NV32_NV10FBSTADD32 0x00600800
628 #define NV32_RASTER 0x00600808
629 #define NV32_NV10CURADD32 0x0060080c
630 #define NV32_CURCONF 0x00600810
631 #define NV32_PANEL_PWR 0x0060081c
632 #define NV32_FUNCSEL 0x00600860
633 
634 /* secondary head */
635 #define NV8_ATTR2INDW 0x006033c0
636 #define NV8_ATTR2DATW 0x006033c0
637 #define NV8_ATTR2DATR 0x006033c1
638 #define NV8_CRTC2IND 0x006033d4
639 #define NV16_CRTC2IND 0x006033d4
640 #define NV8_CRTC2DAT 0x006033d5
641 #define NV8_2INSTAT1 0x006033da // verify!!!
642 #define NV32_NV10FB2STADD32 0x00602800
643 #define NV32_RASTER2 0x00602808
644 #define NV32_NV10CUR2ADD32 0x0060280c
645 #define NV32_2CURCONF 0x00602810
646 #define NV32_2PANEL_PWR 0x0060281c // verify!!!
647 #define NV32_2FUNCSEL 0x00602860
648 
649 /* both heads */
650 #define NVACC_NV11_CRTC_LO 0x00600830
651 #define NVACC_NV11_CRTC_HI 0x00600834
652 
653 /* Nvidia DAC direct registers (standard VGA palette RAM registers) */
654 /* primary head */
655 #define NV8_PALMASK 0x006813c6
656 #define NV8_PALINDR 0x006813c7
657 #define NV8_PALINDW 0x006813c8
658 #define NV8_PALDATA 0x006813c9
659 /* secondary head */
660 #define NV8_PAL2MASK 0x006833c6
661 #define NV8_PAL2INDR 0x006833c7
662 #define NV8_PAL2INDW 0x006833c8
663 #define NV8_PAL2DATA 0x006833c9
664 
665 /* Nvidia PCI direct DAC registers (32bit) */
666 /* primary head */
667 #define NVDAC_CURPOS 0x00680300
668 #define NVDAC_NV10_CURSYNC 0x00680404
669 #define NVDAC_PIXPLLC 0x00680508
670 #define NVDAC_PLLSEL 0x0068050c
671 #define NVDAC_OUTPUT 0x0068052c
672 #define NVDAC_PIXPLLC2 0x00680578
673 #define NVDAC_GENCTRL 0x00680600
674 #define NVDAC_TSTCTRL 0x00680608
675 #define NVDAC_TSTDATA 0x00680610
676 #define NVDAC_TV_SETUP 0x00680700
677 /* (flatpanel registers: confirmed for TNT2 and up) */
678 #define NVDAC_FP_VDISPEND 0x00680800
679 #define NVDAC_FP_VTOTAL 0x00680804
680 #define NVDAC_FP_VCRTC 0x00680808
681 #define NVDAC_FP_VSYNC_S 0x0068080c
682 #define NVDAC_FP_VSYNC_E 0x00680810
683 #define NVDAC_FP_VVALID_S 0x00680814
684 #define NVDAC_FP_VVALID_E 0x00680818
685 #define NVDAC_FP_HDISPEND 0x00680820
686 #define NVDAC_FP_HTOTAL 0x00680824
687 #define NVDAC_FP_HCRTC 0x00680828
688 #define NVDAC_FP_HSYNC_S 0x0068082c
689 #define NVDAC_FP_HSYNC_E 0x00680830
690 #define NVDAC_FP_HVALID_S 0x00680834
691 #define NVDAC_FP_HVALID_E 0x00680838
692 #define NVDAC_FP_CHKSUM 0x00680840
693 #define NVDAC_FP_TST_CTRL 0x00680844
694 #define NVDAC_FP_TG_CTRL 0x00680848
695 #define NVDAC_FP_DEBUG0 0x00680880
696 #define NVDAC_FP_DEBUG1 0x00680884
697 #define NVDAC_FP_DEBUG2 0x00680888
698 #define NVDAC_FP_DEBUG3 0x0068088c
699 #define NVDAC_FP_TMDS_CTRL 0x006808b0
700 #define NVDAC_FP_TMDS_DATA 0x006808b4
701 /* secondary head */
702 #define NVDAC2_CURPOS 0x00682300
703 #define NVDAC2_NV10_CURSYNC 0x00682404
704 #define NVDAC2_PIXPLLC 0x00680520
705 #define NVDAC2_OUTPUT 0x0068252c
706 #define NVDAC2_PIXPLLC2 0x0068057c
707 #define NVDAC2_GENCTRL 0x00682600
708 #define NVDAC2_TSTCTRL 0x00682608
709 #define NVDAC2_TV_SETUP 0x00682700
710 /* (flatpanel registers) */
711 #define NVDAC2_FP_VDISPEND 0x00682800
712 #define NVDAC2_FP_VTOTAL 0x00682804
713 #define NVDAC2_FP_VCRTC 0x00682808
714 #define NVDAC2_FP_VSYNC_S 0x0068280c
715 #define NVDAC2_FP_VSYNC_E 0x00682810
716 #define NVDAC2_FP_VVALID_S 0x00682814
717 #define NVDAC2_FP_VVALID_E 0x00682818
718 #define NVDAC2_FP_HDISPEND 0x00682820
719 #define NVDAC2_FP_HTOTAL 0x00682824
720 #define NVDAC2_FP_HCRTC 0x00682828
721 #define NVDAC2_FP_HSYNC_S 0x0068282c
722 #define NVDAC2_FP_HSYNC_E 0x00682830
723 #define NVDAC2_FP_HVALID_S 0x00682834
724 #define NVDAC2_FP_HVALID_E 0x00682838
725 #define NVDAC2_FP_CHKSUM 0x00682840
726 #define NVDAC2_FP_TST_CTRL 0x00682844
727 #define NVDAC2_FP_TG_CTRL 0x00682848
728 #define NVDAC2_FP_DEBUG0 0x00682880
729 #define NVDAC2_FP_DEBUG1 0x00682884
730 #define NVDAC2_FP_DEBUG2 0x00682888
731 #define NVDAC2_FP_DEBUG3 0x0068288c
732 #define NVDAC2_FP_TMDS_CTRL 0x006828b0 // verify!!!
733 #define NVDAC2_FP_TMDS_DATA 0x006828b4 // verify!!!
734 
735 /* Nvidia CRTC indexed registers */
736 /* VGA standard registers: */
737 #define NVCRTCX_HTOTAL 0x00
738 #define NVCRTCX_HDISPE 0x01
739 #define NVCRTCX_HBLANKS 0x02
740 #define NVCRTCX_HBLANKE 0x03
741 #define NVCRTCX_HSYNCS 0x04
742 #define NVCRTCX_HSYNCE 0x05
743 #define NVCRTCX_VTOTAL 0x06
744 #define NVCRTCX_OVERFLOW 0x07
745 #define NVCRTCX_PRROWSCN 0x08
746 #define NVCRTCX_MAXSCLIN 0x09
747 #define NVCRTCX_VGACURCTRL 0x0a
748 #define NVCRTCX_FBSTADDH 0x0c
749 #define NVCRTCX_FBSTADDL 0x0d
750 #define NVCRTCX_VSYNCS 0x10
751 #define NVCRTCX_VSYNCE 0x11
752 #define NVCRTCX_VDISPE 0x12
753 #define NVCRTCX_PITCHL 0x13
754 #define NVCRTCX_VBLANKS 0x15
755 #define NVCRTCX_VBLANKE 0x16
756 #define NVCRTCX_MODECTL 0x17
757 #define NVCRTCX_LINECOMP 0x18
758 /* Nvidia specific registers: */
759 #define NVCRTCX_REPAINT0 0x19
760 #define NVCRTCX_REPAINT1 0x1a
761 #define NVCRTCX_FIFO 0x1b
762 #define NVCRTCX_LOCK 0x1f
763 #define NVCRTCX_FIFO_LWM 0x20
764 #define NVCRTCX_BUFFER 0x21
765 #define NVCRTCX_LSR 0x25
766 #define NVCRTCX_PIXEL 0x28
767 #define NVCRTCX_HEB 0x2d
768 #define NVCRTCX_CURCTL2 0x2f
769 #define NVCRTCX_CURCTL1 0x30
770 #define NVCRTCX_CURCTL0 0x31
771 #define NVCRTCX_LCD 0x33
772 #define NVCRTCX_RD_I2CBUS_1 0x36
773 #define NVCRTCX_WR_I2CBUS_1 0x37
774 #define NVCRTCX_RMA 0x38
775 #define NVCRTCX_INTERLACE 0x39
776 #define NVCRTCX_TREG 0x3d
777 #define NVCRTCX_RD_I2CBUS_0 0x3e
778 #define NVCRTCX_WR_I2CBUS_0 0x3f
779 #define NVCRTCX_EXTRA 0x41
780 #define NVCRTCX_OWNER 0x44
781 #define NVCRTCX_FP_HTIMING 0x53
782 #define NVCRTCX_FP_VTIMING 0x54
783 #define NVCRTCX_0x59 0x59
784 #define NVCRTCX_0x9f 0x9f
785 
786 /* Nvidia ATTRIBUTE indexed registers */
787 /* VGA standard registers: */
788 #define NVATBX_MODECTL 0x10
789 #define NVATBX_OSCANCOLOR 0x11
790 #define NVATBX_COLPLANE_EN 0x12
791 #define NVATBX_HORPIXPAN 0x13
792 #define NVATBX_COLSEL 0x14
793 
794 /* Nvidia SEQUENCER indexed registers */
795 /* VGA standard registers: */
796 #define NVSEQX_RESET 0x00
797 #define NVSEQX_CLKMODE 0x01
798 #define NVSEQX_MEMMODE 0x04
799 
800 /* Nvidia GRAPHICS indexed registers */
801 /* VGA standard registers: */
802 #define NVGRPHX_ENSETRESET 0x01
803 #define NVGRPHX_DATAROTATE 0x03
804 #define NVGRPHX_READMAPSEL 0x04
805 #define NVGRPHX_MODE 0x05
806 #define NVGRPHX_MISC 0x06
807 #define NVGRPHX_BITMASK 0x08
808 
809 /* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so
810  * RIVA128(ZX)) */
811 #define NVBES_NV04_INTE 0x00680140
812 #define NVBES_NV04_ISCALVH 0x00680200
813 #define NVBES_NV04_CTRL_V 0x00680204
814 #define NVBES_NV04_CTRL_H 0x00680208
815 #define NVBES_NV04_OE_STATE 0x00680224
816 #define NVBES_NV04_SU_STATE 0x00680228
817 #define NVBES_NV04_RM_STATE 0x0068022c
818 #define NVBES_NV04_DSTREF 0x00680230
819 #define NVBES_NV04_DSTSIZE 0x00680234
820 #define NVBES_NV04_FIFOTHRS 0x00680238
821 #define NVBES_NV04_FIFOBURL 0x0068023c
822 #define NVBES_NV04_COLKEY 0x00680240
823 #define NVBES_NV04_GENCTRL 0x00680244
824 #define NVBES_NV04_RED_AMP 0x00680280
825 #define NVBES_NV04_GRN_AMP 0x00680284
826 #define NVBES_NV04_BLU_AMP 0x00680288
827 #define NVBES_NV04_SAT 0x0068028c
828 /* buffer 0 */
829 #define NVBES_NV04_0BUFADR 0x0068020c
830 #define NVBES_NV04_0SRCPTCH 0x00680214
831 #define NVBES_NV04_0OFFSET 0x0068021c
832 /* buffer 1 */
833 #define NVBES_NV04_1BUFADR 0x00680210
834 #define NVBES_NV04_1SRCPTCH 0x00680218
835 #define NVBES_NV04_1OFFSET 0x00680220
836 
837 /* Nvidia BES (Back End Scaler) registers (>= NV10) */
838 #define NVBES_NV10_INTE 0x00008140
839 #define NVBES_NV10_BUFSEL 0x00008700
840 #define NVBES_NV10_GENCTRL 0x00008704
841 #define NVBES_NV10_COLKEY 0x00008b00
842 /* buffer 0 */
843 #define NVBES_NV10_0BUFADR 0x00008900
844 #define NVBES_NV10_0MEMMASK 0x00008908
845 #define NVBES_NV10_0BRICON 0x00008910
846 #define NVBES_NV10_0SAT 0x00008918
847 #define NVBES_NV10_0OFFSET 0x00008920
848 #define NVBES_NV10_0SRCSIZE 0x00008928
849 #define NVBES_NV10_0SRCREF 0x00008930
850 #define NVBES_NV10_0ISCALH 0x00008938
851 #define NVBES_NV10_0ISCALV 0x00008940
852 #define NVBES_NV10_0DSTREF 0x00008948
853 #define NVBES_NV10_0DSTSIZE 0x00008950
854 #define NVBES_NV10_0SRCPTCH 0x00008958
855 /* buffer 1 */
856 #define NVBES_NV10_1BUFADR 0x00008904
857 #define NVBES_NV10_1MEMMASK 0x0000890c
858 #define NVBES_NV10_1BRICON 0x00008914
859 #define NVBES_NV10_1SAT 0x0000891c
860 #define NVBES_NV10_1OFFSET 0x00008924
861 #define NVBES_NV10_1SRCSIZE 0x0000892c
862 #define NVBES_NV10_1SRCREF 0x00008934
863 #define NVBES_NV10_1ISCALH 0x0000893c
864 #define NVBES_NV10_1ISCALV 0x00008944
865 #define NVBES_NV10_1DSTREF 0x0000894c
866 #define NVBES_NV10_1DSTSIZE 0x00008954
867 #define NVBES_NV10_1SRCPTCH 0x0000895c
868 /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
869 #define NVBES_DEC_GENCTRL 0x00001588
870 /* LVDS panel related registers */
871 #define NV32_LVDS_PWR 0x0000130c
872 /* unknown registers */
873 #define NV32_NV4X_WHAT0 0x00001540
874 #define NV32_NV44_WHAT10 0x00001700
875 #define NV32_NV44_WHAT11 0x00001704
876 #define NV32_NV44_WHAT12 0x00001708
877 #define NV32_NV44_WHAT13 0x0000170c
878 
879 /* Macros for convenient accesses to the NV chips */
880 #define NV_REG8(r_) ((vuint8 *) regs)[(r_)]
881 #define NV_REG16(r_) ((vuint16 *) regs)[(r_) >> 1]
882 #define NV_REG32(r_) ((vuint32 *) regs)[(r_) >> 2]
883 
884 /* read and write to PCI config space */
885 #define CFGR(A) \
886  (*(nv_pci_access.offset = NVCFG_##A, \
887  ioctl(fd, NV_GET_PCI, &nv_pci_access, sizeof(nv_pci_access)), \
888  &nv_pci_access.value))
889 #define CFGW(A, B) \
890  (nv_pci_access.offset = NVCFG_##A, nv_pci_access.value = B, \
891  ioctl(fd, NV_SET_PCI, &nv_pci_access, sizeof(nv_pci_access)))
892 
893 /* read and write from ISA I/O space */
894 #define ISAWB(A, B) \
895  (nv_isa_access.adress = A, nv_isa_access.data = (uint8) B, \
896  nv_isa_access.size = 1, \
897  ioctl(fd, NV_ISA_OUT, &nv_isa_access, sizeof(nv_isa_access)))
898 #define ISAWW(A, B) \
899  (nv_isa_access.adress = A, nv_isa_access.data = B, nv_isa_access.size = 2, \
900  ioctl(fd, NV_ISA_OUT, &nv_isa_access, sizeof(nv_isa_access)))
901 #define ISARB(A) \
902  (nv_isa_access.adress = A, \
903  ioctl(fd, NV_ISA_IN, &nv_isa_access, sizeof(nv_isa_access)), \
904  (uint8) nv_isa_access.data)
905 #define ISARW(A) \
906  (nv_isa_access.adress = A, \
907  ioctl(fd, NV_ISA_IN, &nv_isa_access, sizeof(nv_isa_access)), \
908  nv_isa_access.data)
909 
910 /* read and write from the dac registers */
911 #define DACR(A) (NV_REG32(NVDAC_##A))
912 #define DACW(A, B) (NV_REG32(NVDAC_##A) = B)
913 
914 /* read and write from the secondary dac registers */
915 #define DAC2R(A) (NV_REG32(NVDAC2_##A))
916 #define DAC2W(A, B) (NV_REG32(NVDAC2_##A) = B)
917 
918 /* read and write from the backend scaler registers */
919 #define BESR(A) (NV_REG32(NVBES_##A))
920 #define BESW(A, B) (NV_REG32(NVBES_##A) = B)
921 
922 /* read and write from CRTC indexed registers */
923 #define CRTCW(A, B) (NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8)))
924 #define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT))
925 
926 /* read and write from second CRTC indexed registers */
927 #define CRTC2W(A, B) (NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8)))
928 #define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT))
929 
930 /* read and write from ATTRIBUTE indexed registers */
931 #define ATBW(A, B) \
932  (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), \
933  NV_REG8(NV8_ATTRDATW) = (B))
934 #define ATBR(A) \
935  (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), \
936  NV_REG8(NV8_ATTRDATR))
937 
938 /* read and write from ATTRIBUTE indexed registers */
939 #define ATB2W(A, B) \
940  (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), \
941  NV_REG8(NV8_ATTR2DATW) = (B))
942 #define ATB2R(A) \
943  (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), \
944  NV_REG8(NV8_ATTR2DATR))
945 
946 /* read and write from SEQUENCER indexed registers */
947 #define SEQW(A, B) (NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8)))
948 #define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT))
949 
950 /* read and write from PCI GRAPHICS indexed registers */
951 #define GRPHW(A, B) (NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8)))
952 #define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT))
953 
954 /* read and write from the acceleration engine registers */
955 #define ACCR(A) (NV_REG32(NVACC_##A))
956 #define ACCW(A, B) (NV_REG32(NVACC_##A) = B)