The Pedigree Project  0.1
svga_reg.h
1 /*
2  * Copyright (c) 2008-2014, Pedigree Developers
3  *
4  * Please see the CONTRIB file in the root of the source tree for a full
5  * list of contributors.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 /*
21  * Copyright 1998-2001, VMware, Inc.
22  * Distributed under the terms of the MIT License.
23  *
24  */
25 
26 /*
27  * svga_reg.h --
28  *
29  * SVGA hardware definitions
30  */
31 
32 #ifndef _SVGA_REG_H_
33 #define _SVGA_REG_H_
34 
35 /*
36  * Memory and port addresses and fundamental constants
37  */
38 
39 /*
40  * Note-- MAX_WIDTH and MAX_HEIGHT are largely ignored by the code. This
41  * isn't such a bad thing for forward compatibility. --Jeremy.
42  */
43 #define SVGA_MAX_WIDTH 2360
44 #define SVGA_MAX_HEIGHT 1770
45 #define SVGA_MAX_BITS_PER_PIXEL 32
46 #define SVGA_MAX_DEPTH 24
47 
48 #define SVGA_FB_MAX_SIZE \
49  ((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT * SVGA_MAX_BITS_PER_PIXEL / 8) >> \
50  PAGE_SHIFT) + \
51  1) \
52  << PAGE_SHIFT)
53 
54 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
55 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
56 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
57 
58 #define SVGA_MAGIC 0x900000UL
59 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
60 
61 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
62 #define SVGA_VERSION_2 2
63 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
64 
65 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
66  PALETTE_BASE has moved */
67 #define SVGA_VERSION_1 1
68 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
69 
70 /* Version 0 is the initial version */
71 #define SVGA_VERSION_0 0
72 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
73 
74 /* Invalid SVGA_ID_ */
75 #define SVGA_ID_INVALID 0xFFFFFFFF
76 
77 /* More backwards compatibility, old location of color map: */
78 #define SVGA_OLD_PALETTE_BASE 17
79 
80 /* Base and Offset gets us headed the right way for PCI Base Addr Registers */
81 #define SVGA_LEGACY_BASE_PORT 0x4560
82 #define SVGA_INDEX_PORT 0x0
83 #define SVGA_VALUE_PORT 0x1
84 #define SVGA_BIOS_PORT 0x2
85 #define SVGA_NUM_PORTS 0x3
86 
87 /* This port is deprecated, but retained because of old drivers. */
88 #define SVGA_LEGACY_ACCEL_PORT 0x3
89 
90 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
91 #define SVGA_CURSOR_ON_HIDE \
92  0x0 /* Must be 0 to maintain backward compatibility */
93 #define SVGA_CURSOR_ON_SHOW \
94  0x1 /* Must be 1 to maintain backward compatibility */
95 #define SVGA_CURSOR_ON_REMOVE_FROM_FB \
96  0x2 /* Remove the cursor from the framebuffer because we need to see \
97  what's under it */
98 #define SVGA_CURSOR_ON_RESTORE_TO_FB \
99  0x3 /* Put the cursor back in the framebuffer so the user can see it */
100 
101 /*
102  * Registers
103  */
104 
105 enum
106 {
107  SVGA_REG_ID = 0,
108  SVGA_REG_ENABLE = 1,
109  SVGA_REG_WIDTH = 2,
110  SVGA_REG_HEIGHT = 3,
111  SVGA_REG_MAX_WIDTH = 4,
112  SVGA_REG_MAX_HEIGHT = 5,
113  SVGA_REG_DEPTH = 6,
114  SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
115  SVGA_REG_PSEUDOCOLOR = 8,
116  SVGA_REG_RED_MASK = 9,
117  SVGA_REG_GREEN_MASK = 10,
118  SVGA_REG_BLUE_MASK = 11,
119  SVGA_REG_BYTES_PER_LINE = 12,
120  SVGA_REG_FB_START = 13,
121  SVGA_REG_FB_OFFSET = 14,
122  SVGA_REG_VRAM_SIZE = 15,
123  SVGA_REG_FB_SIZE = 16,
124 
125  /* ID 0 implementation only had the above registers, then the palette */
126 
127  SVGA_REG_CAPABILITIES = 17,
128  SVGA_REG_MEM_START = 18, /* Memory for command FIFO and bitmaps */
129  SVGA_REG_MEM_SIZE = 19,
130  SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
131  SVGA_REG_SYNC = 21, /* Write to force synchronization */
132  SVGA_REG_BUSY = 22, /* Read to check if sync is done */
133  SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
134  SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
135  SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
136  SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
137  SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
138  SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
139  SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
140  SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
141  SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
142  SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
143  SVGA_REG_TOP = 33, /* Must be 1 more than the last register */
144 
145  SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
146  /* Next 768 (== 256*3) registers exist for colormap */
147  SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
148  /* Base of scratch registers */
149  /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
150  First 4 are reserved for VESA BIOS Extension; any remaining are for
151  the use of the current SVGA driver. */
152 };
153 
154 /*
155  * Capabilities
156  */
157 
158 #define SVGA_CAP_NONE 0x00000
159 #define SVGA_CAP_RECT_FILL 0x00001
160 #define SVGA_CAP_RECT_COPY 0x00002
161 #define SVGA_CAP_RECT_PAT_FILL 0x00004
162 #define SVGA_CAP_LEGACY_OFFSCREEN 0x00008
163 #define SVGA_CAP_RASTER_OP 0x00010
164 #define SVGA_CAP_CURSOR 0x00020
165 #define SVGA_CAP_CURSOR_BYPASS 0x00040
166 #define SVGA_CAP_CURSOR_BYPASS_2 0x00080
167 #define SVGA_CAP_8BIT_EMULATION 0x00100
168 #define SVGA_CAP_ALPHA_CURSOR 0x00200
169 #define SVGA_CAP_GLYPH 0x00400
170 #define SVGA_CAP_GLYPH_CLIPPING 0x00800
171 #define SVGA_CAP_OFFSCREEN_1 0x01000
172 #define SVGA_CAP_ALPHA_BLEND 0x02000
173 #define SVGA_CAP_3D 0x04000
174 #define SVGA_CAP_EXTENDED_FIFO 0x08000
175 #define SVGA_CAP_MULTIMON 0x10000
176 #define SVGA_CAP_PITCHLOCK 0x20000
177 
178 /*
179  * Raster op codes (same encoding as X) used by FIFO drivers.
180  */
181 
182 #define SVGA_ROP_CLEAR 0x00 /* 0 */
183 #define SVGA_ROP_AND 0x01 /* src AND dst */
184 #define SVGA_ROP_AND_REVERSE 0x02 /* src AND NOT dst */
185 #define SVGA_ROP_COPY 0x03 /* src */
186 #define SVGA_ROP_AND_INVERTED 0x04 /* NOT src AND dst */
187 #define SVGA_ROP_NOOP 0x05 /* dst */
188 #define SVGA_ROP_XOR 0x06 /* src XOR dst */
189 #define SVGA_ROP_OR 0x07 /* src OR dst */
190 #define SVGA_ROP_NOR 0x08 /* NOT src AND NOT dst */
191 #define SVGA_ROP_EQUIV 0x09 /* NOT src XOR dst */
192 #define SVGA_ROP_INVERT 0x0a /* NOT dst */
193 #define SVGA_ROP_OR_REVERSE 0x0b /* src OR NOT dst */
194 #define SVGA_ROP_COPY_INVERTED 0x0c /* NOT src */
195 #define SVGA_ROP_OR_INVERTED 0x0d /* NOT src OR dst */
196 #define SVGA_ROP_NAND 0x0e /* NOT src OR NOT dst */
197 #define SVGA_ROP_SET 0x0f /* 1 */
198 #define SVGA_ROP_UNSUPPORTED 0x10
199 
200 #define SVGA_NUM_SUPPORTED_ROPS 16
201 #define SVGA_ROP_ALL (MASK(SVGA_NUM_SUPPORTED_ROPS))
202 #define SVGA_IS_VALID_ROP(rop) (rop < SVGA_NUM_SUPPORTED_ROPS)
203 
204 /*
205  * Ops
206  * For each pixel, the four channels of the image are computed with:
207  *
208  * C = Ca * Fa + Cb * Fb
209  *
210  * where C, Ca, Cb are the values of the respective channels and Fa
211  * and Fb come from the following table:
212  *
213  * BlendOp Fa Fb
214  * ------------------------------------------
215  * Clear 0 0
216  * Src 1 0
217  * Dst 0 1
218  * Over 1 1-Aa
219  * OverReverse 1-Ab 1
220  * In Ab 0
221  * InReverse 0 Aa
222  * Out 1-Ab 0
223  * OutReverse 0 1-Aa
224  * Atop Ab 1-Aa
225  * AtopReverse 1-Ab Aa
226  * Xor 1-Ab 1-Aa
227  * Add 1 1
228  * Saturate min(1,(1-Ab)/Aa) 1
229  *
230  * Flags
231  * You can use the following flags to achieve additional affects:
232  *
233  * Flag Effect
234  * ------------------------------------------
235  * ConstantSourceAlpha Ca = Ca * Param0
236  * ConstantDestAlpha Cb = Cb * Param1
237  *
238  * Flag effects resolve before the op. For example
239  * BlendOp == Add && Flags == ConstantSourceAlpha |
240  * ConstantDestAlpha results in:
241  *
242  * C = (Ca * Param0) + (Cb * Param1)
243  */
244 
245 #define SVGA_BLENDOP_CLEAR 0
246 #define SVGA_BLENDOP_SRC 1
247 #define SVGA_BLENDOP_DST 2
248 #define SVGA_BLENDOP_OVER 3
249 #define SVGA_BLENDOP_OVER_REVERSE 4
250 #define SVGA_BLENDOP_IN 5
251 #define SVGA_BLENDOP_IN_REVERSE 6
252 #define SVGA_BLENDOP_OUT 7
253 #define SVGA_BLENDOP_OUT_REVERSE 8
254 #define SVGA_BLENDOP_ATOP 9
255 #define SVGA_BLENDOP_ATOP_REVERSE 10
256 #define SVGA_BLENDOP_XOR 11
257 #define SVGA_BLENDOP_ADD 12
258 #define SVGA_BLENDOP_SATURATE 13
259 
260 #define SVGA_NUM_BLENDOPS 14
261 #define SVGA_IS_VALID_BLENDOP(op) (op >= 0 && op < SVGA_NUM_BLENDOPS)
262 
263 #define SVGA_BLENDFLAG_CONSTANT_SOURCE_ALPHA 0x01
264 #define SVGA_BLENDFLAG_CONSTANT_DEST_ALPHA 0x02
265 #define SVGA_NUM_BLENDFLAGS 2
266 #define SVGA_BLENDFLAG_ALL (MASK(SVGA_NUM_BLENDFLAGS))
267 #define SVGA_IS_VALID_BLENDFLAG(flag) ((flag & ~SVGA_BLENDFLAG_ALL) == 0)
268 
269 /*
270  * FIFO offsets (viewed as an array of 32-bit words)
271  */
272 
273 enum
274 {
275  /*
276  * The original defined FIFO offsets
277  */
278 
279  SVGA_FIFO_MIN = 0,
280  SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
281  SVGA_FIFO_NEXT_CMD,
282  SVGA_FIFO_STOP,
283 
284  /*
285  * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
286  */
287 
288  SVGA_FIFO_CAPABILITIES = 4,
289  SVGA_FIFO_FLAGS,
290  SVGA_FIFO_FENCE,
291  SVGA_FIFO_3D_HWVERSION, /* Check SVGA3dHardwareVersion in svga3d_reg.h */
292  SVGA_FIFO_PITCHLOCK,
293 
294  /*
295  * Always keep this last. It's not an offset with semantic value, but
296  * rather a convenient way to produce the value of fifo[SVGA_FIFO_NUM_REGS]
297  */
298 
299  SVGA_FIFO_NUM_REGS
300 };
301 
302 /*
303  * FIFO Capabilities
304  *
305  * Fence -- Fence register and command are supported
306  * Accel Front -- Front buffer only commands are supported
307  * Pitch Lock -- Pitch lock register is supported
308  */
309 
310 #define SVGA_FIFO_CAP_NONE 0
311 #define SVGA_FIFO_CAP_FENCE (1 << 0)
312 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
313 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
314 
315 /*
316  * FIFO Flags
317  *
318  * Accel Front -- Driver should use front buffer only commands
319  */
320 
321 #define SVGA_FIFO_FLAG_NONE 0
322 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
323 
324 /*
325  * Drawing object ID's, in the range 0 to SVGA_MAX_ID
326  */
327 
328 #define SVGA_MAX_ID 499
329 
330 /*
331  * Macros to compute variable length items (sizes in 32-bit words, except
332  * for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes).
333  */
334 
335 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
336 #define SVGA_BITMAP_SCANLINE_SIZE(w) (((w) + 31) >> 5)
337 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
338 #define SVGA_PIXMAP_SCANLINE_SIZE(w, bpp) ((((w) * (bpp)) + 31) >> 5)
339 #define SVGA_GLYPH_SIZE(w, h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
340 #define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
341 
342 /*
343  * Increment from one scanline to the next of a bitmap or pixmap
344  */
345 #define SVGA_BITMAP_INCREMENT(w) ((((w) + 31) >> 5) * sizeof(uint32))
346 #define SVGA_PIXMAP_INCREMENT(w, bpp) \
347  (((((w) * (bpp)) + 31) >> 5) * sizeof(uint32))
348 
349 /*
350  * Transparent color for DRAW_GLYPH_CLIPPED
351  */
352 #define SVGA_COLOR_TRANSPARENT (~0)
353 
354 /*
355  * Commands in the command FIFO
356  */
357 
358 #define SVGA_CMD_INVALID_CMD 0
359 /* FIFO layout:
360  <nothing> (well, undefined) */
361 
362 #define SVGA_CMD_UPDATE 1
363 /* FIFO layout:
364  X, Y, Width, Height */
365 
366 #define SVGA_CMD_RECT_FILL 2
367 /* FIFO layout:
368  Color, X, Y, Width, Height */
369 
370 #define SVGA_CMD_RECT_COPY 3
371 /* FIFO layout:
372  Source X, Source Y, Dest X, Dest Y, Width, Height */
373 
374 #define SVGA_CMD_DEFINE_BITMAP 4
375 /* FIFO layout:
376  Pixmap ID, Width, Height, <scanlines> */
377 
378 #define SVGA_CMD_DEFINE_BITMAP_SCANLINE 5
379 /* FIFO layout:
380  Pixmap ID, Width, Height, Line #, scanline */
381 
382 #define SVGA_CMD_DEFINE_PIXMAP 6
383 /* FIFO layout:
384  Pixmap ID, Width, Height, Depth, <scanlines> */
385 
386 #define SVGA_CMD_DEFINE_PIXMAP_SCANLINE 7
387 /* FIFO layout:
388  Pixmap ID, Width, Height, Depth, Line #, scanline */
389 
390 #define SVGA_CMD_RECT_BITMAP_FILL 8
391 /* FIFO layout:
392  Bitmap ID, X, Y, Width, Height, Foreground, Background */
393 
394 #define SVGA_CMD_RECT_PIXMAP_FILL 9
395 /* FIFO layout:
396  Pixmap ID, X, Y, Width, Height */
397 
398 #define SVGA_CMD_RECT_BITMAP_COPY 10
399 /* FIFO layout:
400  Bitmap ID, Source X, Source Y, Dest X, Dest Y,
401  Width, Height, Foreground, Background */
402 
403 #define SVGA_CMD_RECT_PIXMAP_COPY 11
404 /* FIFO layout:
405  Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */
406 
407 #define SVGA_CMD_FREE_OBJECT 12
408 /* FIFO layout:
409  Object (pixmap, bitmap, ...) ID */
410 
411 #define SVGA_CMD_RECT_ROP_FILL 13
412 /* FIFO layout:
413  Color, X, Y, Width, Height, ROP */
414 
415 #define SVGA_CMD_RECT_ROP_COPY 14
416 /* FIFO layout:
417  Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
418 
419 #define SVGA_CMD_RECT_ROP_BITMAP_FILL 15
420 /* FIFO layout:
421  ID, X, Y, Width, Height, Foreground, Background, ROP */
422 
423 #define SVGA_CMD_RECT_ROP_PIXMAP_FILL 16
424 /* FIFO layout:
425  ID, X, Y, Width, Height, ROP */
426 
427 #define SVGA_CMD_RECT_ROP_BITMAP_COPY 17
428 /* FIFO layout:
429  ID, Source X, Source Y,
430  Dest X, Dest Y, Width, Height, Foreground, Background, ROP */
431 
432 #define SVGA_CMD_RECT_ROP_PIXMAP_COPY 18
433 /* FIFO layout:
434  ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
435 
436 #define SVGA_CMD_DEFINE_CURSOR 19
437 /* FIFO layout:
438 ID, Hotspot X, Hotspot Y, Width, Height,
439 Depth for AND mask, Depth for XOR mask,
440 <scanlines for AND mask>, <scanlines for XOR mask> */
441 
442 #define SVGA_CMD_DISPLAY_CURSOR 20
443 /* FIFO layout:
444 ID, On/Off (1 or 0) */
445 
446 #define SVGA_CMD_MOVE_CURSOR 21
447 /* FIFO layout:
448 X, Y */
449 
450 #define SVGA_CMD_DEFINE_ALPHA_CURSOR 22
451 /* FIFO layout:
452 ID, Hotspot X, Hotspot Y, Width, Height,
453 <scanlines> */
454 
455 #define SVGA_CMD_DRAW_GLYPH 23
456 /* FIFO layout:
457 X, Y, W, H, FGCOLOR, <stencil buffer> */
458 
459 #define SVGA_CMD_DRAW_GLYPH_CLIPPED 24
460 /* FIFO layout:
461 X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer>
462 Transparent color expands are done by setting BGCOLOR to ~0 */
463 
464 #define SVGA_CMD_UPDATE_VERBOSE 25
465 /* FIFO layout:
466 X, Y, Width, Height, Reason */
467 
468 #define SVGA_CMD_SURFACE_FILL 26
469 /* FIFO layout:
470 color, dstSurfaceOffset, x, y, w, h, rop */
471 
472 #define SVGA_CMD_SURFACE_COPY 27
473 /* FIFO layout:
474 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
475 destX, destY, w, h, rop */
476 
477 #define SVGA_CMD_SURFACE_ALPHA_BLEND 28
478 /* FIFO layout:
479 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
480 destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*),
481 param1, param2 */
482 
483 #define SVGA_CMD_FRONT_ROP_FILL 29
484 /* FIFO layout:
485  Color, X, Y, Width, Height, ROP */
486 
487 #define SVGA_CMD_FENCE 30
488 /* FIFO layout:
489  Fence value */
490 
491 #define SVGA_CMD_MAX 31
492 
493 #define SVGA_CMD_MAX_ARGS 64
494 
495 /*
496  * Location and size of SVGA frame buffer and the FIFO.
497  */
498 #define SVGA_VRAM_MAX_SIZE (16 * 1024 * 1024)
499 
500 #define SVGA_VRAM_SIZE_WS (16 * 1024 * 1024) // 16 MB
501 #define SVGA_MEM_SIZE_WS (2 * 1024 * 1024) // 2 MB
502 #define SVGA_VRAM_SIZE_SERVER (4 * 1024 * 1024) // 4 MB
503 #define SVGA_MEM_SIZE_SERVER (256 * 1024) // 256 KB
504 
505 #if /* defined(VMX86_WGS) || */ defined(VMX86_SERVER)
506 #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_SERVER
507 #define SVGA_MEM_SIZE SVGA_MEM_SIZE_SERVER
508 #else
509 #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_WS
510 #define SVGA_MEM_SIZE SVGA_MEM_SIZE_WS
511 #endif
512 
513 /*
514  * SVGA_FB_START is the default starting address of the SVGA frame
515  * buffer in the guest's physical address space.
516  * SVGA_FB_START_BIGMEM is the starting address of the SVGA frame
517  * buffer for VMs that have a large amount of physical memory.
518  *
519  * The address of SVGA_FB_START is set to 2GB - (SVGA_FB_MAX_SIZE +
520  * SVGA_MEM_SIZE), thus the SVGA frame buffer sits at [SVGA_FB_START .. 2GB-1]
521  * in the physical address space. Our older SVGA drivers for NT treat the
522  * address of the frame buffer as a signed integer. For backwards
523  * compatibility, we keep the default location of the frame buffer
524  * at under 2GB in the address space. This restricts VMs to have "only"
525  * up to ~2031MB (i.e., up to SVGA_FB_START) of physical memory.
526  *
527  * For VMs that want more memory than the ~2031MB, we place the SVGA
528  * frame buffer at SVGA_FB_START_BIGMEM. This allows VMs to have up
529  * to 3584MB, at least as far as the SVGA frame buffer is concerned
530  * (note that there may be other issues that limit the VM memory
531  * size). PCI devices use high memory addresses, so we have to put
532  * SVGA_FB_START_BIGMEM low enough so that it doesn't overlap with any
533  * of these devices. Placing SVGA_FB_START_BIGMEM at 0xE0000000
534  * should leave plenty of room for the PCI devices.
535  *
536  * NOTE: All of that is only true for the 0710 chipset. As of the 0405
537  * chipset, the framebuffer start is determined solely based on the value
538  * the guest BIOS or OS programs into the PCI base address registers.
539  */
540 #define SVGA_FB_LEGACY_START 0x7EFC0000
541 #define SVGA_FB_LEGACY_START_BIGMEM 0xE0000000
542 
543 #endif
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