2#ifndef PEDIGREE_PC_PCI_IOAPIC_INTERRUPTS_H
3#define PEDIGREE_PC_PCI_IOAPIC_INTERRUPTS_H
7#if MULTIPROCESSOR && ACPI
9#include "pedigree/kernel/Spinlock.h"
10#include "pedigree/kernel/machine/IrqHandlerRegistry.h"
11#include "pedigree/kernel/machine/ThreadedIrqDispatcher.h"
12#include "pedigree/kernel/processor/InterruptHandler.h"
24 static constexpr uint8_t FirstVector = 0x80;
25 static constexpr size_t VectorCount = 16;
27 PciIoApicInterrupts();
29 bool containsGsi(uint32_t gsi)
const;
30 bool reserveGsi(uint32_t gsi,
bool activeLow);
31 bool initialiseThreaded();
32 bool shutdownThreaded();
38 void enable(irq_id_t
id,
bool enabled);
40 static bool contains(irq_id_t
id) {
41 return id >= FirstVector &&
id < FirstVector + VectorCount;
45 enum class Mode : uint8_t { None, Threaded, Hard };
47 IoApic* controller =
nullptr;
51 Mode mode = Mode::None;
52 bool activeLow =
false;
55 bool removing =
false;
56 bool inFlight =
false;
57 bool quarantined =
false;
61 Mode mode,
bool& routed);
62 static bool findRoute(
Device* device, uint32_t& gsi,
bool& activeLow);
63 void interrupt(
size_t interruptNumber, InterruptState& state)
override;
64 static void dispatchThreaded(
void* context, uint8_t slot,
size_t cookie);
69 IoApic m_Controllers[4];
70 size_t m_ControllerCount;
71 Line m_Lines[VectorCount];
72 uint8_t m_DestinationApicId;
Abstract base class for interrupt-handlers.