The Pedigree Project 0.1
nvme/Registers.h
1/* Copyright (c) 2026, Pedigree Developers. SPDX-License-Identifier: ISC */
2#ifndef NVME_REGISTERS_H
3#define NVME_REGISTERS_H
4#include "pedigree/kernel/processor/types.h"
5
6namespace Nvme {
7constexpr size_t PageSize = 4096;
8constexpr size_t QueueDepth = 16;
9constexpr size_t MaxIoQueues = 8;
10// Bound permanently mapped transfer buffers across all I/O queues.
11constexpr size_t MaxIoSlots = 32;
12constexpr size_t MaxTransfer = 65536;
13enum class VirtualResource : uint8_t { Queue = 0, Interrupt = 1 };
14enum class VirtualizationAction : uint8_t {
15 AllocatePrimary = 1,
16 Offline = 7,
17 Assign = 8,
18 Online = 9,
19};
21 uint32_t flexibleTotal;
22 uint32_t flexibleAssigned;
23 uint16_t flexibleAllocatedToPrimary;
24 uint16_t privateTotal;
25 uint16_t secondaryMaximum;
26 uint16_t preferredGranularity;
27};
29 uint16_t controllerId;
30 uint16_t portId;
31 uint8_t resourceTypes;
34};
36 uint16_t controllerId;
37 uint16_t primaryControllerId;
38 bool online;
39 // The NVMe VF Number is one-based; zero denotes a non-SR-IOV controller.
40 uint16_t virtualFunction;
41 uint16_t queueResources;
42 uint16_t interruptResources;
43};
45 uint8_t count;
46 SecondaryController entries[127];
47};
48enum Register : size_t {
49 Cap = 0x00,
50 Version = 0x08,
51 InterruptMaskSet = 0x0c,
52 InterruptMaskClear = 0x10,
53 Configuration = 0x14,
54 Status = 0x1c,
55 AdminAttributes = 0x24,
56 AdminSubmission = 0x28,
57 AdminCompletion = 0x30,
58 Doorbells = 0x1000,
59};
60struct Command {
61 uint32_t opcode;
62 uint32_t nsid;
63 uint64_t reserved;
64 uint64_t metadata;
65 uint64_t prp1;
66 uint64_t prp2;
67 uint32_t cdw10;
68 uint32_t cdw11;
69 uint32_t cdw12;
70 uint32_t cdw13;
71 uint32_t cdw14;
72 uint32_t cdw15;
73};
74struct Completion {
75 uint32_t result;
76 uint32_t reserved;
77 uint16_t sqHead;
78 uint16_t sqId;
79 uint16_t cid;
80 uint16_t status;
81};
82static_assert(sizeof(Command) == 64);
83static_assert(sizeof(Completion) == 16);
84} // namespace Nvme
85#endif