The Pedigree Project
0.1
src
modules
drivers
common
nvme
nvme/Registers.h
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/* Copyright (c) 2026, Pedigree Developers. SPDX-License-Identifier: ISC */
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#ifndef NVME_REGISTERS_H
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#define NVME_REGISTERS_H
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#include "pedigree/kernel/processor/types.h"
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namespace
Nvme {
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constexpr
size_t
PageSize = 4096;
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constexpr
size_t
QueueDepth = 16;
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constexpr
size_t
MaxIoQueues = 8;
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// Bound permanently mapped transfer buffers across all I/O queues.
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constexpr
size_t
MaxIoSlots = 32;
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constexpr
size_t
MaxTransfer = 65536;
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enum class
VirtualResource : uint8_t { Queue = 0, Interrupt = 1 };
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enum class
VirtualizationAction : uint8_t {
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AllocatePrimary = 1,
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Offline = 7,
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Assign = 8,
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Online = 9,
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};
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struct
VirtualResourceCapabilities
{
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uint32_t flexibleTotal;
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uint32_t flexibleAssigned;
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uint16_t flexibleAllocatedToPrimary;
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uint16_t privateTotal;
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uint16_t secondaryMaximum;
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uint16_t preferredGranularity;
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};
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struct
PrimaryControllerCapabilities
{
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uint16_t controllerId;
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uint16_t portId;
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uint8_t resourceTypes;
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VirtualResourceCapabilities
queues;
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VirtualResourceCapabilities
interrupts;
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};
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struct
SecondaryController
{
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uint16_t controllerId;
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uint16_t primaryControllerId;
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bool
online;
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// The NVMe VF Number is one-based; zero denotes a non-SR-IOV controller.
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uint16_t virtualFunction;
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uint16_t queueResources;
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uint16_t interruptResources;
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};
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struct
SecondaryControllerList
{
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uint8_t count;
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SecondaryController
entries[127];
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};
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enum
Register :
size_t
{
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Cap = 0x00,
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Version = 0x08,
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InterruptMaskSet = 0x0c,
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InterruptMaskClear = 0x10,
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Configuration = 0x14,
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Status = 0x1c,
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AdminAttributes = 0x24,
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AdminSubmission = 0x28,
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AdminCompletion = 0x30,
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Doorbells = 0x1000,
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};
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struct
Command
{
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uint32_t opcode;
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uint32_t nsid;
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uint64_t reserved;
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uint64_t metadata;
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uint64_t prp1;
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uint64_t prp2;
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uint32_t cdw10;
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uint32_t cdw11;
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uint32_t cdw12;
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uint32_t cdw13;
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uint32_t cdw14;
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uint32_t cdw15;
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};
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struct
Completion
{
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uint32_t result;
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uint32_t reserved;
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uint16_t sqHead;
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uint16_t sqId;
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uint16_t cid;
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uint16_t status;
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};
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static_assert
(
sizeof
(
Command
) == 64);
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static_assert
(
sizeof
(
Completion
) == 16);
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}
// namespace Nvme
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#endif
Nvme::Command
Definition
nvme/Registers.h:60
Nvme::Completion
Definition
nvme/Registers.h:74
Nvme::PrimaryControllerCapabilities
Definition
nvme/Registers.h:28
Nvme::SecondaryControllerList
Definition
nvme/Registers.h:44
Nvme::SecondaryController
Definition
nvme/Registers.h:35
Nvme::VirtualResourceCapabilities
Definition
nvme/Registers.h:20
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