The Pedigree Project  0.1
regs.h
1 /*
2  * Copyright (c) 2008-2014, Pedigree Developers
3  *
4  * Please see the CONTRIB file in the root of the source tree for a full
5  * list of contributors.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef __X86EMU_REGS_H
21 #define __X86EMU_REGS_H
22 
23 /*---------------------- Macros and type definitions ----------------------*/
24 
25 #ifdef PACK
26 #pragma PACK
27 #endif
28 
29 /*
30  * General EAX, EBX, ECX, EDX type registers. Note that for
31  * portability, and speed, the issue of byte swapping is not addressed
32  * in the registers. All registers are stored in the default format
33  * available on the host machine. The only critical issue is that the
34  * registers should line up EXACTLY in the same manner as they do in
35  * the 386. That is:
36  *
37  * EAX & 0xff === AL
38  * EAX & 0xffff == AX
39  *
40  * etc. The result is that alot of the calculations can then be
41  * done using the native instruction set fully.
42  */
43 
44 #ifdef __BIG_ENDIAN__
45 
46 typedef struct
47 {
48  u32 e_reg;
49 } I32_reg_t;
50 
51 typedef struct
52 {
53  u16 filler0, x_reg;
54 } I16_reg_t;
55 
56 typedef struct
57 {
58  u8 filler0, filler1, h_reg, l_reg;
59 } I8_reg_t;
60 
61 #else /* !__BIG_ENDIAN__ */
62 
63 typedef struct
64 {
65  u32 e_reg;
66 } I32_reg_t;
67 
68 typedef struct
69 {
70  u16 x_reg;
71 } I16_reg_t;
72 
73 typedef struct
74 {
75  u8 l_reg, h_reg;
76 } I8_reg_t;
77 
78 #endif /* BIG_ENDIAN */
79 
80 typedef union
81 {
82  I32_reg_t I32_reg;
83  I16_reg_t I16_reg;
84  I8_reg_t I8_reg;
86 
88 {
89  i386_general_register A, B, C, D;
90 };
91 
92 typedef struct i386_general_regs Gen_reg_t;
93 
95 {
96  i386_general_register SP, BP, SI, DI, IP;
97  u32 FLAGS;
98 };
99 
100 /*
101  * Segment registers here represent the 16 bit quantities
102  * CS, DS, ES, SS.
103  */
104 
106 {
107  u16 CS, DS, SS, ES, FS, GS;
108 };
109 
110 /* 8 bit registers */
111 #define R_AH gen.A.I8_reg.h_reg
112 #define R_AL gen.A.I8_reg.l_reg
113 #define R_BH gen.B.I8_reg.h_reg
114 #define R_BL gen.B.I8_reg.l_reg
115 #define R_CH gen.C.I8_reg.h_reg
116 #define R_CL gen.C.I8_reg.l_reg
117 #define R_DH gen.D.I8_reg.h_reg
118 #define R_DL gen.D.I8_reg.l_reg
119 
120 /* 16 bit registers */
121 #define R_AX gen.A.I16_reg.x_reg
122 #define R_BX gen.B.I16_reg.x_reg
123 #define R_CX gen.C.I16_reg.x_reg
124 #define R_DX gen.D.I16_reg.x_reg
125 
126 /* 32 bit extended registers */
127 #define R_EAX gen.A.I32_reg.e_reg
128 #define R_EBX gen.B.I32_reg.e_reg
129 #define R_ECX gen.C.I32_reg.e_reg
130 #define R_EDX gen.D.I32_reg.e_reg
131 
132 /* special registers */
133 #define R_SP spc.SP.I16_reg.x_reg
134 #define R_BP spc.BP.I16_reg.x_reg
135 #define R_SI spc.SI.I16_reg.x_reg
136 #define R_DI spc.DI.I16_reg.x_reg
137 #define R_IP spc.IP.I16_reg.x_reg
138 #define R_FLG spc.FLAGS
139 
140 /* special registers */
141 #define R_SP spc.SP.I16_reg.x_reg
142 #define R_BP spc.BP.I16_reg.x_reg
143 #define R_SI spc.SI.I16_reg.x_reg
144 #define R_DI spc.DI.I16_reg.x_reg
145 #define R_IP spc.IP.I16_reg.x_reg
146 #define R_FLG spc.FLAGS
147 
148 /* special registers */
149 #define R_ESP spc.SP.I32_reg.e_reg
150 #define R_EBP spc.BP.I32_reg.e_reg
151 #define R_ESI spc.SI.I32_reg.e_reg
152 #define R_EDI spc.DI.I32_reg.e_reg
153 #define R_EIP spc.IP.I32_reg.e_reg
154 #define R_EFLG spc.FLAGS
155 
156 /* segment registers */
157 #define R_CS seg.CS
158 #define R_DS seg.DS
159 #define R_SS seg.SS
160 #define R_ES seg.ES
161 #define R_FS seg.FS
162 #define R_GS seg.GS
163 
164 /* flag conditions */
165 #define FB_CF 0x0001 /* CARRY flag */
166 #define FB_PF 0x0004 /* PARITY flag */
167 #define FB_AF 0x0010 /* AUX flag */
168 #define FB_ZF 0x0040 /* ZERO flag */
169 #define FB_SF 0x0080 /* SIGN flag */
170 #define FB_TF 0x0100 /* TRAP flag */
171 #define FB_IF 0x0200 /* INTERRUPT ENABLE flag */
172 #define FB_DF 0x0400 /* DIR flag */
173 #define FB_OF 0x0800 /* OVERFLOW flag */
174 
175 /* 80286 and above always have bit#1 set */
176 #define F_ALWAYS_ON (0x0002) /* flag bits always on */
177 
178 /*
179  * Define a mask for only those flag bits we will ever pass back
180  * (via PUSHF)
181  */
182 #define F_MSK \
183  (FB_CF | FB_PF | FB_AF | FB_ZF | FB_SF | FB_TF | FB_IF | FB_DF | FB_OF)
184 
185 /* following bits masked in to a 16bit quantity */
186 
187 #define F_CF 0x0001 /* CARRY flag */
188 #define F_PF 0x0004 /* PARITY flag */
189 #define F_AF 0x0010 /* AUX flag */
190 #define F_ZF 0x0040 /* ZERO flag */
191 #define F_SF 0x0080 /* SIGN flag */
192 #define F_TF 0x0100 /* TRAP flag */
193 #define F_IF 0x0200 /* INTERRUPT ENABLE flag */
194 #define F_DF 0x0400 /* DIR flag */
195 #define F_OF 0x0800 /* OVERFLOW flag */
196 
197 #define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag))
198 #define SET_FLAG(flag) (M.x86.R_FLG |= (flag))
199 #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag))
200 #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag))
201 #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0)
202 
203 #define CONDITIONAL_SET_FLAG(COND, FLAG) \
204  if (COND) \
205  SET_FLAG(FLAG); \
206  else \
207  CLEAR_FLAG(FLAG)
208 
209 #define F_PF_CALC 0x010000 /* PARITY flag has been calced */
210 #define F_ZF_CALC 0x020000 /* ZERO flag has been calced */
211 #define F_SF_CALC 0x040000 /* SIGN flag has been calced */
212 
213 #define F_ALL_CALC 0xff0000 /* All have been calced */
214 
215 /*
216  * Emulator machine state.
217  * Segment usage control.
218  */
219 #define SYSMODE_SEG_DS_SS 0x00000001
220 #define SYSMODE_SEGOVR_CS 0x00000002
221 #define SYSMODE_SEGOVR_DS 0x00000004
222 #define SYSMODE_SEGOVR_ES 0x00000008
223 #define SYSMODE_SEGOVR_FS 0x00000010
224 #define SYSMODE_SEGOVR_GS 0x00000020
225 #define SYSMODE_SEGOVR_SS 0x00000040
226 #define SYSMODE_PREFIX_REPE 0x00000080
227 #define SYSMODE_PREFIX_REPNE 0x00000100
228 #define SYSMODE_PREFIX_DATA 0x00000200
229 #define SYSMODE_PREFIX_ADDR 0x00000400
230 #define SYSMODE_INTR_PENDING 0x10000000
231 #define SYSMODE_EXTRN_INTR 0x20000000
232 #define SYSMODE_HALTED 0x40000000
233 
234 #define SYSMODE_SEGMASK \
235  (SYSMODE_SEG_DS_SS | SYSMODE_SEGOVR_CS | SYSMODE_SEGOVR_DS | \
236  SYSMODE_SEGOVR_ES | SYSMODE_SEGOVR_FS | SYSMODE_SEGOVR_GS | \
237  SYSMODE_SEGOVR_SS)
238 #define SYSMODE_CLRMASK \
239  (SYSMODE_SEG_DS_SS | SYSMODE_SEGOVR_CS | SYSMODE_SEGOVR_DS | \
240  SYSMODE_SEGOVR_ES | SYSMODE_SEGOVR_FS | SYSMODE_SEGOVR_GS | \
241  SYSMODE_SEGOVR_SS | SYSMODE_PREFIX_DATA | SYSMODE_PREFIX_ADDR)
242 
243 #define INTR_SYNCH 0x1
244 #define INTR_ASYNCH 0x2
245 #define INTR_HALTED 0x4
246 
247 typedef struct
248 {
249  struct i386_general_regs gen;
250  struct i386_special_regs spc;
251  struct i386_segment_regs seg;
252  /*
253  * MODE contains information on:
254  * REPE prefix 2 bits repe,repne
255  * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
256  * Delayed flag set 3 bits (zero, signed, parity)
257  * reserved 6 bits
258  * interrupt # 8 bits instruction raised interrupt
259  * BIOS video segregs 4 bits
260  * Interrupt Pending 1 bits
261  * Extern interrupt 1 bits
262  * Halted 1 bits
263  */
264  u32 mode;
265  volatile int intr; /* mask of pending interrupts */
266  int debug;
267 #ifdef DEBUG
268  int check;
269  u16 saved_ip;
270  u16 saved_cs;
271  int enc_pos;
272  int enc_str_pos;
273  char decode_buf[32]; /* encoded byte stream */
274  char decoded_buf[256]; /* disassembled strings */
275 #endif
276  u8 intno;
277  u8 __pad[3];
278 } X86EMU_regs;
279 
280 /****************************************************************************
281 REMARKS:
282 Structure maintaining the emulator machine state.
283 
284 MEMBERS:
285 mem_base - Base real mode memory for the emulator
286 mem_size - Size of the real mode memory block for the emulator
287 private - private data pointer
288 x86 - X86 registers
289 ****************************************************************************/
290 typedef struct
291 {
292  unsigned long mem_base;
293  unsigned long mem_size;
294  void *_private;
295  X86EMU_regs x86;
296 } X86EMU_sysEnv;
297 
298 #ifdef END_PACK
299 #pragma END_PACK
300 #endif
301 
302 /*----------------------------- Global Variables --------------------------*/
303 
304 #ifdef __cplusplus
305 extern "C" { /* Use "C" linkage when in C++ mode */
306 #endif
307 
308 /* Global emulator machine state.
309  *
310  * We keep it global to avoid pointer dereferences in the code for speed.
311  */
312 
313 extern X86EMU_sysEnv _X86EMU_env;
314 #define M _X86EMU_env
315 
316 /*-------------------------- Function Prototypes --------------------------*/
317 
318 /* Function to log information at runtime */
319 
320 void printk(const char *fmt, ...);
321 
322 #ifdef __cplusplus
323 } /* End of "C" linkage for C++ */
324 #endif
325 
326 #endif /* __X86EMU_REGS_H */
Definition: regs.h:63
Definition: regs.h:68
Definition: regs.h:73