BusMasterIde.h

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef BUSMASTERIDE_H
#define BUSMASTERIDE_H

#include "pedigree/kernel/process/Mutex.h"
#include "pedigree/kernel/processor/MemoryRegion.h"
#include "pedigree/kernel/processor/types.h"

class IoBase;

#define BUSMASTER_VERBOSE_LOGGING 0

typedef struct
{
    // First bit = zero
    uint32_t physAddr;

    // First bit = zero
    uint16_t byteCount;

    // Last bit = EOT
    uint16_t rsvdEot;
} __attribute__((packed)) PhysicalRegionDescriptor;

typedef union
{
    uint8_t reg;

    struct
    {
        uint8_t startStop : 1;
        uint8_t rsvd1 : 2;
        uint8_t rwCtl : 1;
        uint8_t rsvd2 : 4;
    } __attribute__((packed)) bits;
} BusMasterIdeCommandRegister;

typedef union
{
    uint8_t reg;
    struct bits
    {
        uint8_t bmIdeActive : 1;
        uint8_t error : 1;
        uint8_t interrupt : 1;
        uint8_t rsvd : 2;
        uint8_t drv0Capable : 1;
        uint8_t drv1Capable : 1;
        uint8_t simplexOnly : 1;
    } __attribute__((packed)) bits;
} BusMasterIdeStatusRegister;

typedef struct
{
    uint32_t baseAddress;
} BusMasterIdeDescriptorTablePointerRegister;

class BusMasterIde
{
  public:
    BusMasterIde();
    virtual ~BusMasterIde();

    bool initialise(IoBase *pBase);

    bool add(uintptr_t buffer, size_t nBytes);

    bool begin(bool bWrite);

    bool hasInterrupt();

    bool hasError();

    bool hasCompleted();

    void commandComplete();

    bool isActive() const
    {
        return m_bActive;
    }

  private:
    IoBase *m_pBase;

    Mutex m_PrdTableLock;

    PhysicalRegionDescriptor *m_PrdTable;

    size_t m_LastPrdTableOffset;

    physical_uintptr_t m_PrdTablePhys;

    MemoryRegion m_PrdTableMemRegion;

    bool m_bActive;

    enum BusMasterIdeRegs
    {
        Command = 0,          // R/W
        DeviceSpecific1 = 1,  // --
        Status = 2,           // R/W/C
        DeviceSpecific2 = 3,  // --
        PrdTableAddr = 4      // R/W
    };
};

#endif