LocalApic.h

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
#ifndef KERNEL_MACHINE_X86_COMMON_LOCAL_APIC_H
#define KERNEL_MACHINE_X86_COMMON_LOCAL_APIC_H
#include <config.h>
 
#if MULTIPROCESSOR
 
#include "pedigree/kernel/Atomic.h"
#include "pedigree/kernel/compiler.h"
#include "pedigree/kernel/machine/SchedulerTimer.h"
#include "pedigree/kernel/processor/InterruptHandler.h"
#include "pedigree/kernel/processor/MemoryMappedIo.h"
#include "pedigree/kernel/processor/Processor.h"
#include "pedigree/kernel/processor/ProcessorInformation.h"
#include "pedigree/kernel/processor/state_forward.h"
#include "pedigree/kernel/processor/types.h"
 
#include "LocalApicTimerHandlerSlots.h"
#include "LocalApicTlbShootdown.h"
 
class SchedulerTimerHandler;
 
#define IPI_TLB_SHOOTDOWN_VECTOR 0xF9
#define IPI_RESCHEDULE_VECTOR 0xFA
#define IPI_PROCESSOR_CONTROL_VECTOR 0xFB
#define ERROR_VECTOR 0xFC
#define SPURIOUS_VECTOR 0xFD
#define TIMER_VECTOR 0xFE
 
class LocalApic : public SchedulerTimer, private InterruptHandler {
 private:
  enum class ProcessorControlState : size_t { Idle, Paused, Unavailable, Terminal };
  enum class ProcessorControlOwnership { Fresh, Quiesced, Failed, Terminal };
 
 public:
  inline LocalApic()
      : m_IoSpace("Local APIC"),
        m_PhysicalAddress(0),
        m_X2Apic(false),
        m_Handlers(),
        m_BusFrequency(0),
        m_TimerState(),
        m_ProcessorControlOwner(),
        m_TlbMutations(),
        m_TlbTerminalFailure(),
        m_TlbShootdown(),
        m_ProcessorControlState(static_cast<size_t>(ProcessorControlState::Idle)),
        m_ControlledProcessorCount(0),
        m_TerminalProcessorCount(0),
        m_TerminalProcessorMask(0) {}
  inline virtual ~LocalApic() {}
 
  bool initialise(uint64_t physicalAddress) INITIALISATION_ONLY;
  void prepareApplicationProcessor() INITIALISATION_ONLY;
  bool initialiseProcessor() INITIALISATION_ONLY;
 
  enum {
    deliveryModeFixed = 0,
    deliveryModeLowestPriority = 1,
    deliveryModeSmi = 2,
    deliveryModeNmi = 4,
    deliveryModeInit = 5,
    deliveryModeStartup = 6,
    deliveryModeExtInt = 7
  };
 
  MUST_USE_RESULT bool interProcessorInterrupt(uint8_t destinationApicId, uint8_t vector,
                                               size_t deliveryMode, bool bAssert,
                                               bool bLevelTriggered);
 
  MUST_USE_RESULT bool interProcessorInterruptAllExcludingThis(uint8_t vector, size_t deliveryMode);
 
  MUST_USE_RESULT TlbInvalidationResult invalidateAllProcessors(void* address,
                                                                uint64_t processors = ~uint64_t(0));
 
  MUST_USE_RESULT TlbInvalidationResult beginTlbInvalidation(bool& global);
 
  void endTlbInvalidation();
 
  MUST_USE_RESULT bool closeTlbInvalidationAdmissionForTerminalFailure(
      TlbInvalidationResult result);
 
  bool tlbInvalidationFailureActive() const;
  bool tlbInvalidationTerminal() const;
 
  void servicePendingTlbShootdown();
 
  void servicePendingTerminalProcessorControl();
 
  enum class ProcessorControlResult {
    Success,
    InvalidState,
    SubmissionFailed,
    AcknowledgementTimedOut,
    DrainTimedOut
  };
 
  MUST_USE_RESULT ProcessorControlResult quiesceAllOtherProcessors(size_t expectedProcessors);
 
  MUST_USE_RESULT ProcessorControlResult resumeAllOtherProcessors();
 
  MUST_USE_RESULT ProcessorControlResult haltAllOtherProcessors(size_t expectedProcessors);
 
  uint8_t getId();
 
  //
  // SchedulerTimer interface
  //
  uint64_t nominalQuantumNs() const override;
  bool supportsOneShot() const override {
    return true;
  }
  bool armDeadline(uint64_t absoluteMonotonicNs) override;
  void disarm() override;
  virtual bool registerHandler(SchedulerTimerHandler* handler) {
    // Logical Processor::id() is assigned after early BSP timer setup and
    // can change during topology construction. The LAPIC's raw physical
    // identifier is already stable on both sides of that transition.
    return m_Handlers.registerHandler(getId(), handler);
  }
 
  virtual bool removeHandler(SchedulerTimerHandler* handler) {
    return canRemoveHandlerInCurrentContext() && m_Handlers.removeHandler(getId(), handler);
  }
 
  void ack();
 
 private:
  LocalApic(const LocalApic&);
  LocalApic& operator=(const LocalApic&);
 
  bool check(uint64_t physicalAddress) INITIALISATION_ONLY;
 
  bool waitForIcrIdle();
  bool submitIcr(uint32_t high, uint32_t low);
  uint32_t readRegister(uint32_t offset);
  void writeRegister(uint32_t value, uint32_t offset);
 
  ProcessorControlState processorControlState() const;
  bool acquireProcessorControlOwner(bool acceptRetained, ProcessorControlOwnership& ownership);
  bool releaseProcessorControlOwner();
  ProcessorControlResult completeTerminalControl(size_t expectedProcessors);
  ProcessorControlResult retainTerminalControl(ProcessorControlResult result);
  bool acquireTlbShootdownBarrier();
  bool releaseTlbShootdownBarrier();
  bool adoptTerminalTlbShootdownBarrier();
  bool waitForTlbMutationDrain();
  bool waitForProcessorCount(size_t expectedProcessors);
  bool waitForTerminalProcessorCount(size_t expectedProcessors);
  bool waitForProcessorDrain();
  ProcessorControlResult retainFailedControl(ProcessorControlResult result);
  ProcessorControlResult releaseProcessorControlOrRetainFailure(ProcessorControlResult released,
                                                                ProcessorControlResult retained);
  ProcessorControlResult retainQuiescedControl(ProcessorControlResult result);
  ProcessorControlResult finishFailedQuiesce(ProcessorControlResult result);
  ProcessorControlResult unwindQuiesce(ProcessorControlResult failure);
  bool markTerminalProcessor(size_t processor);
  void enterTerminalProcessorControl() NORETURN;
 
  //
  // InterruptHandler interface
  //
  virtual void interrupt(size_t nInterruptNumber, InterruptState& state);
 
  MemoryMappedIo m_IoSpace;
  uint64_t m_PhysicalAddress;
  bool m_X2Apic;
 
  LocalApicTimerHandlerSlots m_Handlers;
 
  size_t m_BusFrequency;
 
  struct TimerState {
    uint64_t lastInterruptNs;
    bool oneShot;
    uint64_t armedDeadlineNs;
  };
  TimerState m_TimerState[LocalApicTimerHandlerSlots::Capacity];
 
  LocalApicProcessorControlOwner m_ProcessorControlOwner;
 
  LocalApicTlbMutationGate m_TlbMutations;
  LocalApicTlbTerminalFailure m_TlbTerminalFailure;
  LocalApicTlbShootdown m_TlbShootdown;
 
  Atomic<size_t> m_ProcessorControlState;
 
  Atomic<size_t> m_ControlledProcessorCount;
 
  Atomic<size_t> m_TerminalProcessorCount;
  Atomic<uint64_t> m_TerminalProcessorMask;
};
 
#endif
 
#endif