main_beagle.cc

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

// C++ entry point

#include "Elf32.h"
#include "support.h"

// autogen.h contains the full kernel binary in a char array
#include "autogen.h"

extern "C" {
volatile unsigned char *uart1 = (volatile unsigned char *) 0x4806A000;
volatile unsigned char *uart2 = (volatile unsigned char *) 0x4806C000;
volatile unsigned char *uart3 = (volatile unsigned char *) 0x49020000;
};

// http://www.simtec.co.uk/products/SWLINUX/files/booting_article.html
// http://www.arm.linux.org.uk/developer/booting.php

#define ATAG_NONE 0
#define ATAG_CORE 0x54410001
#define ATAG_MEM 0x54410002
#define ATAG_VIDEOTEXT 0x54410003
#define ATAG_RAMDISK 0x54410004
#define ATAG_INITRD2 0x54410005
#define ATAG_SERIAL 0x54410006
#define ATAG_REVISION 0x54410007
#define ATAG_VIDEOLFB 0x54410008
#define ATAG_CMDLINE 0x54410009

struct atag_header
{
    uint32_t size;
    uint32_t tag;
};

struct atag_core
{
    uint32_t flags;
    uint32_t pagesize;
    uint32_t rootdev;
};

struct atag_mem
{
    uint32_t size;
    uint32_t start;
};

struct atag_videotext
{
    unsigned char x;
    unsigned char y;
    unsigned short video_page;
    unsigned char video_mode;
    unsigned char video_cols;
    unsigned short video_ega_bx;
    unsigned char video_lines;
    unsigned char video_isvga;
    unsigned short video_points;
};

struct atag_ramdisk
{
    uint32_t flags;
    uint32_t size;
    uint32_t start;
};

struct atag_initrd2
{
    uint32_t start;
    uint32_t size;
};

struct atag_serialnr
{
    uint32_t low;
    uint32_t high;
};

struct atag_revision
{
    uint32_t rev;
};

struct atag_videolfb
{
    unsigned short lfb_width;
    unsigned short lfb_height;
    unsigned short lfb_depth;
    unsigned short lfb_linelength;
    uint32_t lfb_base;
    uint32_t lfb_size;
    unsigned char red_size;
    unsigned char red_pos;
    unsigned char green_size;
    unsigned char green_pos;
    unsigned char blue_size;
    unsigned char blue_pos;
    unsigned char rsvd_size;
    unsigned char rsvd_pos;
};

struct atag_cmdline
{
    char cmdline[1];  // Minimum size.
};

struct atag
{
    struct atag_header hdr;
    union
    {
        struct atag_core core;
        struct atag_mem mem;
        struct atag_videotext videotext;
        struct atag_ramdisk ramdisk;
        struct atag_initrd2 initrd2;
        struct atag_serialnr serialnr;
        struct atag_revision revision;
        struct atag_videolfb videolfb;
        struct atag_cmdline cmdline;
    } u;
};

#define MULTIBOOT_FLAG_MEM 0x001
#define MULTIBOOT_FLAG_DEVICE 0x002
#define MULTIBOOT_FLAG_CMDLINE 0x004
#define MULTIBOOT_FLAG_MODS 0x008
#define MULTIBOOT_FLAG_AOUT 0x010
#define MULTIBOOT_FLAG_ELF 0x020
#define MULTIBOOT_FLAG_MMAP 0x040
#define MULTIBOOT_FLAG_CONFIG 0x080
#define MULTIBOOT_FLAG_LOADER 0x100
#define MULTIBOOT_FLAG_APM 0x200
#define MULTIBOOT_FLAG_VBE 0x400

struct BootstrapStruct_t
{
    uint32_t flags;

    uint32_t mem_lower;
    uint32_t mem_upper;

    uint32_t boot_device;

    uint32_t cmdline;

    uint32_t mods_count;
    uint32_t mods_addr;

    /* ELF information */
    uint32_t num;
    uint32_t size;
    uint32_t addr;
    uint32_t shndx;

    uint32_t mmap_length;
    uint32_t mmap_addr;

    uint32_t drives_length;
    uint32_t drives_addr;

    uint32_t config_table;

    uint32_t boot_loader_name;

    uint32_t apm_table;

    uint32_t vbe_control_info;
    uint32_t vbe_mode_info;
    uint32_t vbe_mode;
    uint32_t vbe_interface_seg;
    uint32_t vbe_interface_off;
    uint32_t vbe_interface_len;
} __attribute__((packed));


#define DLL_REG 0x00         // R/W
#define RHR_REG 0x00         // R
#define THR_REG 0x00         // W
#define DLH_REG 0x04         // R/W
#define IER_REG 0x04         // R/W
#define IIR_REG 0x08         // R
#define FCR_REG 0x08         // W
#define EFR_REG 0x08         // RW
#define LCR_REG 0x0C         // RW
#define MCR_REG 0x10         // RW
#define XON1_ADDR1_REG 0x10  // RW
#define LSR_REG 0x14         // R
#define XON2_ADDR2_REG 0x14  // RW
#define MSR_REG 0x18         // R
#define TCR_REG 0x18         // RW
#define XOFF1_REG 0x18       // RW
#define SPR_REG 0x1C         // RW
#define TLR_REG 0x1C         // RW
#define XOFF2_REG 0x1C       // RW
#define MDR1_REG 0x20        // RW
#define MDR2_REG 0x24        // RW

#define USAR_REG 0x38  // R

#define SCR_REG 0x40  // RW
#define SSR_REG 0x44  // R

#define MVR_REG 0x50   // R
#define SYSC_REG 0x54  // RW
#define SYSS_REG 0x58  // R
#define WER_REG 0x5C   // RW

extern "C" volatile unsigned char *uart_get(int n)
{
    if (n == 1)
        return uart1;
    else if (n == 2)
        return uart2;
    else if (n == 3)
        return uart3;
    else
        return 0;
}

extern "C" bool uart_softreset(int n)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return false;

    // 1. Initiate a software reset
    uart[SYSC_REG] |= 0x2;

    // 2. Wait for the end of the reset operation
    while (!(uart[SYSS_REG] & 0x1))
        ;

    return true;
}

extern "C" bool uart_fifodefaults(int n)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return false;

    // 1. Switch to configuration mode B to access the EFR_REG register
    unsigned char old_lcr_reg = uart[LCR_REG];
    uart[LCR_REG] = 0xBF;

    // 2. Enable submode TCR_TLR to access TLR_REG (part 1 of 2)
    unsigned char efr_reg = uart[EFR_REG];
    unsigned char old_enhanced_en = efr_reg & 0x8;
    if (!(efr_reg & 0x8))  // Set ENHANCED_EN (bit 4) if not set
        efr_reg |= 0x8;
    uart[EFR_REG] = efr_reg;  // Write back to the register

    // 3. Switch to configuration mode A
    uart[LCR_REG] = 0x80;

    // 4. Enable submode TCL_TLR to access TLR_REG (part 2 of 2)
    unsigned char mcr_reg = uart[MCR_REG];
    unsigned char old_tcl_tlr = mcr_reg & 0x20;
    if (!(mcr_reg & 0x20))
        mcr_reg |= 0x20;
    uart[MCR_REG] = mcr_reg;

    // 5. Enable FIFO, load new FIFO triggers (part 1 of 3), and the new DMA
    // mode (part 1 of 2)
    uart[FCR_REG] = 1;  // TX and RX FIFO triggers at 8 characters, no DMA mode

    // 6. Switch to configuration mode B to access EFR_REG
    uart[LCR_REG] = 0xBF;

    // 7. Load new FIFO triggers (part 2 of 3)
    uart[TLR_REG] = 0;

    // 8. Load new FIFO triggers (part 3 of 3) and the new DMA mode (part 2 of
    // 2)
    uart[SCR_REG] = 0;

    // 9. Restore the ENHANCED_EN value saved in step 2
    if (!old_enhanced_en)
        uart[EFR_REG] = uart[EFR_REG] ^ 0x8;

    // 10. Switch to configuration mode A to access the MCR_REG register
    uart[LCR_REG] = 0x80;

    // 11. Restore the MCR_REG TCR_TLR value saved in step 4
    if (!old_tcl_tlr)
        uart[MCR_REG] = uart[MCR_REG] ^ 0x20;

    // 12. Restore the LCR_REG value stored in step 1
    uart[LCR_REG] = old_lcr_reg;

    return true;
}

extern "C" bool uart_protoconfig(int n)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return false;

    // 1. Disable UART to access DLL_REG and DLH_REG
    uart[MDR1_REG] = (uart[MDR1_REG] & ~0x7) | 0x7;

    // 2. Switch to configuration mode B to access the EFR_REG register
    uart[LCR_REG] = 0xBF;

    // 3. Enable access to IER_REG
    unsigned char efr_reg = uart[EFR_REG];
    unsigned char old_enhanced_en = efr_reg & 0x8;
    if (!(efr_reg & 0x8))  // Set ENHANCED_EN (bit 4) if not set
        efr_reg |= 0x8;
    uart[EFR_REG] = efr_reg;  // Write back to the register

    // 4. Switch to operational mode to access the IER_REG register
    uart[LCR_REG] = 0;

    // 5. Clear IER_REG
    uart[IER_REG] = 0;

    // 6. Switch to configuration mode B to access DLL_REG and DLH_REG
    uart[LCR_REG] = 0xBF;

    // 7. Load the new divisor value (looking for 115200 baud)
    uart[0x0] = 0x1A;  // divisor low byte
    uart[0x4] = 0;     // divisor high byte

    // 8. Switch to operational mode to access the IER_REG register
    uart[LCR_REG] = 0;

    // 9. Load new interrupt configuration
    uart[IER_REG] = 0;  // No interrupts wanted at this stage

    // 10. Switch to configuration mode B to access the EFR_REG register
    uart[LCR_REG] = 0xBF;

    // 11. Restore the ENHANCED_EN value saved in step 3
    if (old_enhanced_en)
        uart[EFR_REG] = uart[EFR_REG] ^ 0x8;

    // 12. Load the new protocol formatting (parity, stop bit, character length)
    // and enter operational mode
    uart[LCR_REG] = 0x3;  // 8 bit characters, no parity, one stop bit

    // 13. Load the new UART mode
    uart[MDR1_REG] = 0;

    return true;
}

extern "C" bool uart_disableflowctl(int n)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return false;

    // 1. Switch to configuration mode A to access the MCR_REG register
    unsigned char old_lcr_reg = uart[LCR_REG];
    uart[LCR_REG] = 0x80;

    // 2. Enable submode TCR_TLR to access TCR_REG (part 1 of 2)
    unsigned char mcr_reg = uart[MCR_REG];
    unsigned char old_tcl_tlr = mcr_reg & 0x20;
    if (!(mcr_reg & 0x20))
        mcr_reg |= 0x20;
    uart[MCR_REG] = mcr_reg;

    // 3. Switch to configuration mode B to access the EFR_REG register
    uart[LCR_REG] = 0xBF;

    // 4. Enable submode TCR_TLR to access the TCR_REG register (part 2 of 2)
    unsigned char efr_reg = uart[EFR_REG];
    unsigned char old_enhanced_en = efr_reg & 0x8;
    if (!(efr_reg & 0x8))  // Set ENHANCED_EN (bit 4) if not set
        efr_reg |= 0x8;
    uart[EFR_REG] = efr_reg;  // Write back to the register

    // 5. Load new start and halt trigger values
    uart[TCR_REG] = 0;

    // 6. Disable RX/TX hardware flow control mode, and restore the ENHANCED_EN
    // values stored in step 4
    uart[EFR_REG] = 0;

    // 7. Switch to configuration mode A to access MCR_REG
    uart[LCR_REG] = 0x80;

    // 8. Restore the MCR_REG TCR_TLR value stored in step 2
    if (!old_tcl_tlr)
        uart[MCR_REG] = uart[MCR_REG] ^ 0x20;

    // 9. Restore the LCR_REG value saved in step 1
    uart[LCR_REG] = old_lcr_reg;

    return true;
}

extern "C" void uart_write(int n, char c)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return;

    // Wait until the hold register is empty
    while (!(uart[LSR_REG] & 0x20))
        ;
    uart[THR_REG] = c;
}

extern "C" char uart_read(int n)
{
    volatile unsigned char *uart = uart_get(n);
    if (!uart)
        return 0;

    // Wait for data in the receive FIFO
    while (!(uart[LSR_REG] & 0x1))
        ;
    return uart[RHR_REG];
}

extern "C" inline void writeStr(int n, const char *str)
{
    char c;
    while ((c = *str++))
        uart_write(n, c);
}

extern "C" void writeHex(int uart, unsigned int n)
{
    bool noZeroes = true;

    int i;
    unsigned int tmp;
    for (i = 28; i > 0; i -= 4)
    {
        tmp = (n >> i) & 0xF;
        if (tmp == 0 && noZeroes)
            continue;

        if (tmp >= 0xA)
        {
            noZeroes = false;
            uart_write(uart, tmp - 0xA + 'a');
        }
        else
        {
            noZeroes = false;
            uart_write(uart, tmp + '0');
        }
    }

    tmp = n & 0xF;
    if (tmp >= 0xA)
        uart_write(uart, tmp - 0xA + 'a');
    else
        uart_write(uart, tmp + '0');
}

class BeagleGpio
{
  public:
    BeagleGpio()
        : m_gpio1(0), m_gpio2(0), m_gpio3(0), m_gpio4(0), m_gpio5(0), m_gpio6(0)
    {
    }
    ~BeagleGpio()
    {
    }

    void initialise()
    {
        m_gpio1 = (volatile unsigned int *) 0x48310000;
        initspecific(1, m_gpio1);
        m_gpio2 = (volatile unsigned int *) 0x49050000;
        initspecific(2, m_gpio2);
        m_gpio3 = (volatile unsigned int *) 0x49052000;
        initspecific(3, m_gpio3);
        m_gpio4 = (volatile unsigned int *) 0x49054000;
        initspecific(4, m_gpio4);
        m_gpio5 = (volatile unsigned int *) 0x49056000;
        initspecific(5, m_gpio5);
        m_gpio6 = (volatile unsigned int *) 0x49058000;
        initspecific(6, m_gpio6);
    }

    void clearpin(int pin)
    {
        // Grab the GPIO MMIO range for the pin
        int base = 0;
        volatile unsigned int *gpio = getGpioForPin(pin, &base);
        if (!gpio)
        {
            writeStr(3, "BeagleGpio::drivepin : No GPIO found for pin ");
            writeHex(3, pin);
            writeStr(3, "!\r\n");
            return;
        }

        // Write to the CLEARDATAOUT register
        gpio[0x24] = (1 << base);
    }

    void drivepin(int pin)
    {
        // Grab the GPIO MMIO range for the pin
        int base = 0;
        volatile unsigned int *gpio = getGpioForPin(pin, &base);
        if (!gpio)
        {
            writeStr(3, "BeagleGpio::drivepin : No GPIO found for pin ");
            writeHex(3, pin);
            writeStr(3, "!\r\n");
            return;
        }

        // Write to the SETDATAOUT register. We can set a specific bit in
        // this register without needing to maintain the state of a full
        // 32-bit register (zeroes have no effect).
        gpio[0x25] = (1 << base);
    }

    bool pinstate(int pin)
    {
        // Grab the GPIO MMIO range for the pin
        int base = 0;
        volatile unsigned int *gpio = getGpioForPin(pin, &base);
        if (!gpio)
        {
            writeStr(3, "BeagleGpio::pinstate : No GPIO found for pin ");
            writeHex(3, pin);
            writeStr(3, "!\r\n");
            return false;
        }

        return (gpio[0x25] & (1 << base));
    }

    int capturepin(int pin)
    {
        // Grab the GPIO MMIO range for the pin
        int base = 0;
        volatile unsigned int *gpio = getGpioForPin(pin, &base);
        if (!gpio)
        {
            writeStr(3, "BeagleGpio::capturepin :No GPIO found for pin ");
            writeHex(3, pin);
            writeStr(3, "!\r\n");
            return 0;
        }

        // Read the data from the pin
        return (gpio[0xE] & (1 << base)) >> (base ? base - 1 : 0);
    }

    void enableoutput(int pin)
    {
        // Grab the GPIO MMIO range for the pin
        int base = 0;
        volatile unsigned int *gpio = getGpioForPin(pin, &base);
        if (!gpio)
        {
            writeStr(3, "BeagleGpio::enableoutput :No GPIO found for pin ");
            writeHex(3, pin);
            writeStr(3, "!\r\n");
            return;
        }

        // Set the pin as an output (if it's an input, the bit is set)
        if (gpio[0xD] & (1 << base))
            gpio[0xD] ^= (1 << base);
    }

  private:
    void initspecific(int n, volatile unsigned int *gpio)
    {
        if (!gpio)
            return;

        // Write information about it
        unsigned int rev = gpio[0];
        writeStr(3, "GPIO");
        writeHex(3, n);
        writeStr(3, ": revision ");
        writeHex(3, (rev & 0xF0) >> 4);
        writeStr(3, ".");
        writeHex(3, rev & 0x0F);
        writeStr(3, " - initialising: ");

        // 1. Perform a software reset of the GPIO.
        gpio[0x4] = 2;
        while (!(gpio[0x5] & 1))
            ;  // Poll GPIO_SYSSTATUS, bit 0

        // 2. Disable all IRQs
        gpio[0x7] = 0;  // GPIO_IRQENABLE1
        gpio[0xB] = 0;  // GPIO_IRQENABLE2

        // 3. Enable the module
        gpio[0xC] = 0;

        // Completed the reset and initialisation.
        writeStr(3, "Done.\r\n");
    }

    volatile unsigned int *getGpioForPin(int pin, int *bit)
    {
        volatile unsigned int *gpio = 0;
        if (pin < 32)
        {
            *bit = pin;
            gpio = m_gpio1;
        }
        else if ((pin >= 34) && (pin < 64))
        {
            *bit = pin - 34;
            gpio = m_gpio2;
        }
        else if ((pin >= 64) && (pin < 96))
        {
            *bit = pin - 64;
            gpio = m_gpio3;
        }
        else if ((pin >= 96) && (pin < 128))
        {
            *bit = pin - 96;
            gpio = m_gpio4;
        }
        else if ((pin >= 128) && (pin < 160))
        {
            *bit = pin - 128;
            gpio = m_gpio5;
        }
        else if ((pin >= 160) && (pin < 192))
        {
            *bit = pin - 160;
            gpio = m_gpio6;
        }
        else
            gpio = 0;
        return gpio;
    }

    volatile unsigned int *m_gpio1;
    volatile unsigned int *m_gpio2;
    volatile unsigned int *m_gpio3;
    volatile unsigned int *m_gpio4;
    volatile unsigned int *m_gpio5;
    volatile unsigned int *m_gpio6;
};

struct FirstLevelDescriptor
{

    union
    {
        struct
        {
            uint32_t type : 2;
            uint32_t ignore : 30;
        } PACKED fault;
        struct
        {
            uint32_t type : 2;
            uint32_t sbz1 : 1;
            uint32_t ns : 1;
            uint32_t sbz2 : 1;
            uint32_t domain : 4;
            uint32_t imp : 1;
            uint32_t baseaddr : 22;
        } PACKED pageTable;
        struct
        {
            uint32_t type : 2;
            uint32_t b : 1;
            uint32_t c : 1;
            uint32_t xn : 1;
            uint32_t domain : 4;  
            uint32_t imp : 1;
            uint32_t ap1 : 2;
            uint32_t tex : 3;
            uint32_t ap2 : 1;
            uint32_t s : 1;
            uint32_t nG : 1;
            uint32_t sectiontype : 1;  
            uint32_t ns : 1;
            uint32_t base : 12;
        } PACKED section;

        uint32_t entry;
    } descriptor;
} PACKED;

struct SecondLevelDescriptor
{

    union
    {
        struct
        {
            uint32_t type : 2;
            uint32_t ignore : 30;
        } PACKED fault;
        struct
        {
            uint32_t type : 2;
            uint32_t b : 1;
            uint32_t c : 1;
            uint32_t ap1 : 2;
            uint32_t sbz : 3;
            uint32_t ap2 : 1;
            uint32_t s : 1;
            uint32_t nG : 1;
            uint32_t tex : 3;
            uint32_t xn : 1;
            uint32_t base : 16;
        } PACKED largepage;
        struct
        {
            uint32_t type : 2;
            uint32_t b : 1;
            uint32_t c : 1;
            uint32_t ap1 : 2;
            uint32_t sbz : 3;
            uint32_t ap2 : 1;
            uint32_t s : 1;
            uint32_t nG : 1;
            uint32_t base : 20;
        } PACKED smallpage;

        uint32_t entry;
    } descriptor;
} PACKED;

extern "C" void __start(uint32_t r0, uint32_t machineType, struct atag *tagList)
    __attribute__((noreturn));
void __start(uint32_t r0, uint32_t machineType, struct atag *tagList)
{
    BeagleGpio gpio;

    bool b = uart_softreset(3);
    if (!b)
        while (1)
            ;
    b = uart_fifodefaults(3);
    if (!b)
        while (1)
            ;
    b = uart_protoconfig(3);
    if (!b)
        while (1)
            ;
    b = uart_disableflowctl(3);
    if (!b)
        while (1)
            ;

    writeStr(3, "Pedigree for the BeagleBoard\r\n\r\n");

    gpio.initialise();

    gpio.enableoutput(149);
    gpio.enableoutput(150);

    gpio.drivepin(
        149);  // Switch on the USR1 LED to show we're active and thinking
    gpio.clearpin(150);

    writeStr(
        3, "\r\nPlease press the USER button on the board to continue.\r\n");

    while (!gpio.capturepin(7))
        ;

    writeStr(3, "USER button pressed, continuing...\r\n\r\n");

    writeStr(
        3, "Press 1 to toggle the USR0 LED, and 2 to toggle the USR1 "
           "LED.\r\nPress 0 to clear both LEDs. Hit ENTER to boot the "
           "kernel.\r\n");
    while (1)
    {
        char c = uart_read(3);
        if (c == '1')
        {
            writeStr(3, "Toggling USR0 LED\r\n");
            if (gpio.pinstate(150))
                gpio.clearpin(150);
            else
                gpio.drivepin(150);
        }
        else if (c == '2')
        {
            writeStr(3, "Toggling USR1 LED\r\n");
            if (gpio.pinstate(149))
                gpio.clearpin(149);
            else
                gpio.drivepin(149);
        }
        else if (c == '0')
        {
            writeStr(3, "Clearing both USR0 and USR1 LEDs\r\n");
            gpio.clearpin(149);
            gpio.clearpin(150);
        }
        else if ((c == 13) || (c == 10))
            break;
    }

    writeStr(3, "\r\n\r\nPlease wait while the kernel is loaded...\r\n");

    Elf32 elf("kernel");
    writeStr(3, "Preparing file... ");
    elf.load((uint8_t *) file, 0);
    writeStr(3, "Done!\r\n");

    writeStr(3, "Loading file into memory (please wait) ");
    elf.writeSections();
    writeStr(3, " Done!\r\n");
    int (*main)(struct BootstrapStruct_t *) =
        (int (*)(struct BootstrapStruct_t *)) elf.getEntryPoint();

    struct BootstrapStruct_t *bs =
        reinterpret_cast<struct BootstrapStruct_t *>(0x80008000);
    writeStr(3, "Creating bootstrap information structure... ");
    ByteSet(bs, 0, sizeof(*bs));
    bs->shndx = elf.m_pHeader->shstrndx;
    bs->num = elf.m_pHeader->shnum;
    bs->size = elf.m_pHeader->shentsize;
    bs->addr = (unsigned int) elf.m_pSectionHeaders;
    bs->flags |= MULTIBOOT_FLAG_ELF;

    // Repurpose these variables a little....
    bs->mods_addr = reinterpret_cast<uint32_t>(elf.m_pBuffer);
    bs->mods_count = (sizeof file) + 0x1000;
    bs->flags |= MULTIBOOT_FLAG_MODS;

    // For every section header, set .addr = .offset + m_pBuffer.
    for (int i = 0; i < elf.m_pHeader->shnum; i++)
    {
        elf.m_pSectionHeaders[i].addr =
            elf.m_pSectionHeaders[i].offset + (uint32_t) elf.m_pBuffer;
    }
    writeStr(3, "Done!\r\n");

    // Just before running the kernel proper, turn off both LEDs so we can use
    // their states for debugging the kernel.
    gpio.clearpin(149);
    gpio.clearpin(150);

    // Run the kernel, finally
    writeStr(
        3, "Now starting the Pedigree kernel (can take a while, please "
           "wait).\r\n\r\n");
    main(bs);

    while (1)
    {
        asm volatile("wfi");
    }
}