x86_common/ProcessorInformation.cc

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
#include "pedigree/kernel/process/InfoBlock.h"
#include "pedigree/kernel/process/PerProcessorScheduler.h"
#include "pedigree/kernel/process/Process.h"
#include "pedigree/kernel/process/Thread.h"
#include "pedigree/kernel/processor/Processor.h"
#include "pedigree/kernel/processor/VirtualAddressSpace.h"
#include "pedigree/kernel/processor/state.h"
#include "pedigree/kernel/processor/types.h"
#include "pedigree/kernel/processor/x64/tss.h"
#include "pedigree/kernel/processor/x86_common/ProcessorInformation.h"
#include "pedigree/kernel/utilities/new"
 
VirtualAddressSpace& X86CommonProcessorInformation::getVirtualAddressSpace() const {
  if (m_VirtualAddressSpace)
    return *m_VirtualAddressSpace;
  else
    return VirtualAddressSpace::getKernelAddressSpace();
}
void X86CommonProcessorInformation::setVirtualAddressSpace(
    VirtualAddressSpace& virtualAddressSpace) {
  m_VirtualAddressSpace = &virtualAddressSpace;
}
 
void X86CommonProcessorInformation::setTssSelector(uint16_t TssSelector) {
  m_TssSelector = TssSelector;
}
void X86CommonProcessorInformation::setTss(void* Tss) {
  m_Tss = reinterpret_cast<TaskStateSegment*>(Tss);
}
uint16_t X86CommonProcessorInformation::getTssSelector() const {
  return m_TssSelector;
}
void* X86CommonProcessorInformation::getTss() const {
  return reinterpret_cast<void*>(m_Tss);
}
uint16_t X86CommonProcessorInformation::getTlsSelector() {
  return m_TlsSelector;
}
void X86CommonProcessorInformation::setTlsSelector(uint16_t tls) {
  m_TlsSelector = tls;
}
 
uintptr_t X86CommonProcessorInformation::getKernelStack() const {
  return m_Tss->rsp0;
}
void X86CommonProcessorInformation::setKernelStack(uintptr_t stack) {
#if X64
  // Event-stack retirement and scheduling must not leave a borrowed frame behind.
  pedigree_materialize_user_entry();
#endif
  m_Tss->rsp0 = stack;
#if X64
  m_KernelGsAnchor.kernelStack = stack;
#endif
}
 
#if X64
void X86CommonProcessorInformation::activateKernelGsAnchor(size_t processorIndex) {
  m_KernelGsAnchor.processorIndex = processorIndex;
  const uintptr_t entry = reinterpret_cast<uintptr_t>(&m_KernelGsAnchor);
  uint32_t eax = entry, edx = entry >> 32;
  // Kernel GS stays local to the CPU; the alternate MSR belongs to userspace.
  asm volatile("wrmsr" ::"a"(eax), "d"(edx), "c"(0xc0000101) : "memory");
}
#endif
 
void X86CommonProcessorInformation::setCurrentThread(Thread* pThread) {
  if (m_RcuState.active()) {
    panic("Context switch inside an RCU read section.");
  }
#if X64
  if (m_pCurrentThread)
    m_pCurrentThread->saveUserGsBase();
#endif
  m_pCurrentThread = pThread;
#if X64
  Processor::setUserGsBase(pThread->getUserGsBase());
#endif
  InfoBlockManager::instance().setPid(pThread->getParent()->getId());
}
 
PerProcessorScheduler& X86CommonProcessorInformation::getScheduler() {
  // Allocate the scheduler lazily.
  if (m_Scheduler == nullptr) {
    m_Scheduler = new PerProcessorScheduler();
  }
  return *m_Scheduler;
}
 
void X86CommonProcessorInformation::initialiseTscClockAnchor(uint64_t tsc, uint64_t nanoseconds) {
  __atomic_store_n(&m_TscClockAnchor, tsc, __ATOMIC_RELAXED);
  __atomic_store_n(&m_TscClockAnchorNanoseconds, nanoseconds, __ATOMIC_RELAXED);
  __atomic_store_n(&m_TscClockAnchorInitialised, true, __ATOMIC_RELEASE);
}
 
X86CommonProcessorInformation::X86CommonProcessorInformation(ProcessorId processorId,
                                                             uint8_t apicId)
    : m_ProcessorId(processorId),
      m_TssSelector(0),
      m_Tss(0),
      m_VirtualAddressSpace(&VirtualAddressSpace::getKernelAddressSpace()),
      m_LocalApicId(apicId),
      m_pCurrentThread(0),
      m_Scheduler(nullptr),
      m_TlsSelector(0),
      m_DeviceHardIrqDepth(0),
      m_TscClockAnchor(0),
      m_TscClockAnchorNanoseconds(0),
      m_TscClockAnchorInitialised(false) {}
X86CommonProcessorInformation::~X86CommonProcessorInformation() {
  delete m_Scheduler;
}
 
void X86CommonProcessorInformation::setIds(ProcessorId processorId, uint8_t apicId) {
  m_ProcessorId = processorId;
  m_LocalApicId = apicId;
}