Pic.h

/*
 * Copyright (c) 2008-2014, Pedigree Developers
 *
 * Please see the CONTRIB file in the root of the source tree for a full
 * list of contributors.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
#ifndef KERNEL_MACHINE_X86_COMMON_PIC_H
#define KERNEL_MACHINE_X86_COMMON_PIC_H
#include "pedigree/kernel/compiler.h"
#include "pedigree/kernel/machine/IrqDiagnosticSnapshotStore.h"
#include "pedigree/kernel/machine/IrqHandler.h"
#include "pedigree/kernel/machine/IrqHandlerRegistry.h"
#include "pedigree/kernel/machine/IrqManager.h"
#include "pedigree/kernel/machine/ThreadedIrqDispatcher.h"
#include "pedigree/kernel/machine/types.h"
#include "pedigree/kernel/process/Mutex.h"
#include "pedigree/kernel/processor/InterruptHandler.h"
#include "pedigree/kernel/processor/IoPort.h"
#include "pedigree/kernel/processor/state_forward.h"
#include "pedigree/kernel/processor/types.h"
#include "pedigree/kernel/utilities/new"
 
#include <config.h>
 
#include "PicIrqState.h"
 
class Device;
class HardIrqHandler;
class IrqHandler;
class IrqHandlerBase;
class SchedulerIrqHandler;
class PciMessageInterrupts;
class PciIoApicInterrupts;
 
class Pic : public IrqManager, private InterruptHandler {
 public:
  inline static Pic& instance() {
    return m_Instance;
  }
 
  bool reservePciRoute(uint8_t irq);
 
  EXPORTED_PUBLIC bool hasIoApic() const;
  EXPORTED_PUBLIC bool reservePciGsi(uint32_t gsi, bool activeLow);
 
  //
  // IrqManager interface
  //
  virtual irq_id_t registerIsaIrqHandler(uint8_t irq, IrqHandler* handler, const IrqPolicy& policy);
  virtual irq_id_t registerPciIrqHandler(IrqHandler* handler, Device* pDevice,
                                         const IrqPolicy& policy);
  virtual irq_id_t registerHardIsaIrqHandler(uint8_t irq, HardIrqHandler* handler,
                                             const IrqPolicy& policy);
  virtual irq_id_t registerHardPciIrqHandler(HardIrqHandler* handler, Device* pDevice,
                                             const IrqPolicy& policy);
  irq_id_t registerPciMessageIrqHandler(IrqHandler* handler, Device* device,
                                        const IrqPolicy& intxFallbackPolicy) override;
  bool registerPciMsixIrqHandlers(Device* device, IrqHandler* const* handlers, size_t count,
                                  irq_id_t* ids, bool& fallbackSafe,
                                  const size_t* processors = nullptr) override;
  irq_id_t registerHardPciMessageIrqHandler(HardIrqHandler* handler, Device* device,
                                            const IrqPolicy& intxFallbackPolicy) override;
  virtual irq_id_t registerSchedulerIrqHandler(uint8_t irq, SchedulerIrqHandler* handler,
                                               const IrqPolicy& policy);
  virtual bool unregisterSchedulerIrqHandler(irq_id_t Id, SchedulerIrqHandler* handler);
  virtual bool unregisterHandler(irq_id_t Id, IrqHandlerBase* handler);
  virtual size_t snapshotIrqLines(IrqLineDiagnosticSnapshot* out, size_t capacity) const;
 
  bool initialise() INITIALISATION_ONLY;
 
  bool initialiseThreaded();
 
  bool shutdownThreaded();
 
  virtual void tick();
 
  virtual bool control(uint8_t irq, ControlCode code, size_t argument);
 
 private:
  class StateGuard;
  class HardStateGuard;
 
  Pic() INITIALISATION_ONLY;
  inline virtual ~Pic() {}
  Pic(const Pic&);
  Pic& operator=(const Pic&);
 
  //
  // InterruptHandler interface
  //
  virtual void interrupt(size_t interruptNumber, InterruptState& state);
 
  static void dispatchThreadedLine(void* context, uint8_t irq, size_t cookie);
#if MULTIPROCESSOR
  static bool promptThreadedWorker(void* context, uint8_t line, size_t workerProcessor);
#endif
  static constexpr uint8_t ControllerWorkLine = PicIrqState::LineCount;
  bool drainOnePendingControllerBatchLocked();
  void drainPendingControllerActionsLocked();
  void releaseControllerState();
  void releaseControllerStateFromInterrupt();
  bool handControllerStateToWorker();
  void finishDeferredLineTransitionsLocked();
  void clearControllerTemporaryMaskLocked(uint16_t restoreMask = 0xFFFF);
  uint16_t effectiveMaskLocked() const;
  void beginLineTransitionLocked(uint8_t irq);
  void finishLineTransitionLocked(uint8_t irq);
  void finishHandlerUnregisterLocked(uint8_t irq, IrqHandlerRegistry::UnregisterResult result,
                                     IrqHandlerRegistry::LineMode removedDelivery);
  bool claimPciTriggerLocked(uint8_t irq);
  void restorePciTriggerLocked(uint8_t irq);
  void admitThreadedOccurrenceLocked(uint8_t irq);
  void finishHardDispatchLocked(const PicHardTailRecord& record);
  void finishHardDispatchFromInterrupt(const PicHardTailRecord& record);
  size_t advanceThreadedCookieLocked(uint8_t irq);
  void publishDiagnosticLineLocked(uint8_t irq);
  void publishAllDiagnosticLinesLocked();
 
  enum FailClosedReason : uint8_t {
    HardHandoffQuarantine = 1U << 0,
    ThreadedPublicationQuarantine = 1U << 1,
    UnhandledQuarantine = 1U << 2,
    ControllerContentionQuarantine = 1U << 3,
  };
 
  void eoiLocked(uint8_t irq);
  void applyMaskLocked();
  void setEnabledLocked(uint8_t irq, bool enable);
  void enable(uint8_t irq, bool enable);
  void enableAll(bool enable);
 
  bool spuriousLocked(size_t irq);
 
  IoPort m_SlavePort;
  IoPort m_MasterPort;
  IoPort m_ElcrPort;
  uint16_t m_OwnedElcr;
  uint16_t m_OriginalElcr;
 
  IrqHandlerRegistry m_Handlers;
#if MULTIPROCESSOR
  PciMessageInterrupts* m_Messages;
#if ACPI
  PciIoApicInterrupts* m_Intx;
#endif
#endif
  SchedulerIrqHandler* m_SchedulerIrqHandler;
  PicIrqState m_IrqState;
  PicControllerStateGate m_ControllerStateGate;
  PicHardTailQueue m_HardTailQueue;
  Mutex m_ControllerThreadMutex;
  ThreadedIrqDispatcher m_ThreadedDispatcher;
  size_t m_ThreadedCookies[PicIrqState::LineCount];
  size_t m_ThreadedDispatchGenerations[PicIrqState::LineCount];
  size_t m_HardStageGenerations[PicIrqState::LineCount];
  bool m_ThreadedHadHardStage[PicIrqState::LineCount];
  bool m_ThreadedHardAdmitted[PicIrqState::LineCount];
  HardIrqDisposition m_ThreadedHardDisposition[PicIrqState::LineCount];
  bool m_ThreadedHardVetoRecovery[PicIrqState::LineCount];
  size_t m_ThreadedHardVetoRecoveryGenerations[PicIrqState::LineCount];
  uint8_t m_FailClosedReasons[PicIrqState::LineCount];
  size_t m_ThreadedPublicationFailures[PicIrqState::LineCount];
  size_t m_RemovalRejections[PicIrqState::LineCount];
  size_t m_ControllerContentions[PicIrqState::LineCount];
  size_t m_ControllerPromptAttempts;
  size_t m_ControllerPromptFailures;
  size_t m_ControllerPromptDestination;
  size_t m_ControllerPromptState;
  uint16_t m_ControllerTemporaryMask;
  uint16_t m_AppliedControllerMask;
  uint16_t m_DeferredLineTransitions;
  size_t m_DeliveryProcessor;
  uint8_t m_DeliveryApicId;
  IrqDiagnosticSnapshotStore<PicIrqState::LineCount> m_Diagnostics;
  size_t m_UnregisterReservations[PicIrqState::LineCount];
  bool m_ShuttingDown;
  size_t m_IrqCount[16];
  size_t m_SpuriousIrqCount[16];
  size_t m_UnhandledIrqCount[16];
  bool m_MitigatedIrqs[16];
  size_t m_MitigationThreshold[16];
  static EXPORTED_PUBLIC Pic m_Instance;
};
 
#endif